Hitachi SH7750 Hardware Manual page 526

T1 Tw T2
CKIO
A25–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.75 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
Rev. 6.0, 07/02, page 476 of 986