Figure 13.17 Basic Dram Access Timing - Hitachi SH7750 Hardware Manual

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and
Tc2 the read data latch cycle.
CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Rev. 6.0, 07/02, page 400 of 986
Tr1 Tr2
Row

Figure 13.17 Basic DRAM Access Timing

Tc1 Tc2
Column
Tpc