CLK
A25–A0
D63–D0
DTR
MD = 01
CMD
DQMn
ID1, ID0
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device → → → → External Bus Data Transfer
CA
CA
D0
D1
WT
WT
Idle cycle
CA
D3
WT
Idle cycle
Idle cycle
Rev. 6.0, 07/02, page 565 of 986