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Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Also See for SH7750

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Table of Contents

21
Table of Contents
43
Table of Contents
- 51
  Overview
- 51
  SH7750 Series (SH7750, SH7750S, SH7750R) Features
- 53
  Table 1.1 SH7750 Series Features
- 59
  Block Diagram
- 59
  Figure 1.1 Block Diagram of SH7750 Series Functions
- 60
  Figure 1.2 Pin Arrangement (256-Pin BGA)
- 60
  Pin Arrangement
- 61
  Figure 1.3 Pin Arrangement (208-Pin QFP)
- 62
  Figure 1.4 Pin Arrangement (264-Pin CSP)
- 63
  Pin Functions
  - 63
    Pin Functions (256-Pin BGA)
  - 63
    Table 1.2 Pin Functions
  - 73
    Pin Functions (208-Pin QFP)
  - 73
    Table 1.3 Pin Functions
  - 81
    Pin Functions (264-Pin CSP)
  - 81
    Table 1.4 Pin Functions
- 91
  Data Formats
- 91
  Programming Model
- 92
  Register Configuration
  - 92
    Privileged Mode and Banks
  - 93
    Table 2.1 Initial Register Values
    - 94
      Appendix H Power-On and Power-Off Procedures
    - 94
      Appendix Iproduct Code Lineup
- 94
  Figure 2.2 CPU Register Configuration in Each Processor Mode
  - 95
    General Registers
  - 96
    Figure 2.3 General Registers
  - 97
    Floating-Point Registers
  - 98
    Figure 2.4 Floating-Point Registers
  - 99
    Control Registers
  - 100
    System Registers
- 94
  Index
- 102
  Memory-Mapped Registers
- 103
  Data Format in Registers
- 103
  Data Formats in Memory
- 103
  Figure 2.1 Data Formats
- 103
  Figure 2.5 Data Formats in Memory
- 104
  Processor States
- 105
  Figure 2.6 Processor State Transitions
- 105
  Processor Modes
- 107
  Memory Management Unit (MMU)
- 107
  Overview
  - 107
    Features
  - 107
    Role of the MMU
  - 109
    Figure 3.1 Role of the MMU
  - 110
    Register Configuration
  - 110
    Caution
  - 110
    Table 3.1 MMU Registers
- 111
  Figure 3.2 Mmu-Related Registers
- 111
  Register Descriptions
- 114
  Address Space
  - 114
    Physical Address Space
  - 115
    Figure 3.3 Physical Address Space (MMUCR.AT = 0)
  - 116
    Figure 3.4 P4 Area
  - 117
    External Memory Space
  - 117
    Figure 3.5 External Memory Space
  - 118
    Virtual Address Space
  - 118
    Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
  - 119
    On-Chip RAM Space
  - 119
    Address Translation
  - 120
    Single Virtual Memory Mode and Multiple Virtual Memory Mode
  - 120
    Address Space Identifier (ASID)
- 121
  TLB Functions
  - 121
    Unified TLB (UTLB) Configuration
  - 121
    Figure 3.7 UTLB Configuration
  - 122
    Figure 3.8 Relationship Between Page Size and Address Format
  - 125
    Instruction TLB (ITLB) Configuration
  - 125
    Address Translation Method
  - 125
    Figure 3.9 ITLB Configuration
  - 126
    Figure 3.10 Flowchart of Memory Access Using UTLB
  - 127
    Figure 3.11 Flowchart of Memory Access Using ITLB
- 128
  MMU Functions
  - 128
    MMU Hardware Management
  - 128
    MMU Software Management
  - 128
    MMU Instruction (LDTLB)
  - 129
    Hardware ITLB Miss Handling
  - 129
    Figure 3.12 Operation of LDTLB Instruction
  - 130
    Avoiding Synonym Problems
- 131
  MMU Exceptions
  - 131
    Instruction TLB Multiple Hit Exception
  - 132
    Instruction TLB Miss Exception
  - 133
    Instruction TLB Protection Violation Exception
  - 134
    Data TLB Multiple Hit Exception
  - 134
    Data TLB Miss Exception
  - 135
    Data TLB Protection Violation Exception
  - 136
    Initial Page Write Exception
- 137
  Memory-Mapped TLB Configuration
  - 138
    ITLB Address Array
  - 138
    Figure 3.13 Memory-Mapped ITLB Address Array
  - 139
    ITLB Data Array 1
  - 139
    Figure 3.14 Memory-Mapped ITLB Data Array 1
  - 140
    ITLB Data Array 2
  - 140
    UTLB Address Array
  - 140
    Figure 3.15 Memory-Mapped ITLB Data Array 2
  - 141
    Figure 3.16 Memory-Mapped UTLB Address Array
  - 142
    UTLB Data Array 1
  - 142
    Figure 3.17 Memory-Mapped UTLB Data Array 1
  - 143
    UTLB Data Array 2
  - 143
    Figure 3.18 Memory-Mapped UTLB Data Array 2
- 145
  Caches
- 145
  Overview
  - 145
    Features
  - 145
    Table 4.1 Cache Features (SH7750, SH7750S)
  - 145
    Table 4.2 Cache Features (SH7750R)
  - 146
    Register Configuration
  - 146
    Table 4.3 Features of Store Queues
  - 146
    Table 4.4 Cache Control Registers
- 147
  Figure 4.1 Cache and Store Queue Control Registers
- 147
  Register Descriptions
- 149
  Operand Cache (OC)
  - 149
    Configuration
  - 150
    Figure 4.2 Configuration of Operand Cache(Sh7750, SH7750S)
  - 151
    Figure 4.3 Configuration of Operand Cache (SH7750R)
  - 153
    Read Operation
  - 154
    Write Operation
  - 155
    Write-Back Buffer
  - 155
    Write-Through Buffer
  - 155
    Figure 4.4 Configuration of Write-Back Buffer
  - 155
    Figure 4.5 Configuration of Write-Through Buffer
  - 156
    RAM Mode
  - 157
    OC Index Mode
  - 157
    Coherency Between Cache and External Memory
- 158
  Instruction Cache (IC)
  - 158
    Configuration
  - 159
    Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
  - 160
    Figure 4.7 Configuration of Instruction Cache (SH7750R)
  - 161
    Read Operation
  - 161
    IC Index Mode
- 162
  Memory-Mapped Cache Configuration (SH7750, SH7750S)
  - 162
    IC Address Array
  - 163
    IC Data Array
  - 163
    Figure 4.8 Memory-Mapped IC Address Array
  - 164
    OC Address Array
  - 164
    Figure 4.9 Memory-Mapped IC Data Array
  - 165
    OC Data Array
  - 165
    Figure 4.10 Memory-Mapped OC Address Array
- 166
  Figure 4.11 Memory-Mapped OC Data Array
  - 167
    IC Address Array
  - 168
    IC Data Array
  - 168
    Figure 4.12 Memory-Mapped IC Address Array
  - 169
    OC Address Array
  - 169
    Figure 4.13 Memory-Mapped IC Data Array
  - 170
    OC Data Array
  - 170
    Figure 4.14 Memory-Mapped OC Address Array
  - 171
    Summary of the Memory-Mapping of the OC
  - 171
    Figure 4.15 Memory-Mapped OC Data Array
- 166
  Memory-Mapped Cache Configuration (SH7750R)
- 172
  Store Queues
  - 172
    SQ Configuration
  - 172
    SQ Writes
  - 172
    Transfer to External Memory
  - 172
    Figure 4.16 Store Queue Configuration
  - 174
    SQ Protection
  - 174
    Reading the Sqs (SH7750R Only)
  - 175
    SQ Usage Notes
- 177
  Exceptions
- 177
  Overview
  - 177
    Features
  - 177
    Register Configuration
  - 177
    Table 5.1 Exception-Related Registers
- 178
  Figure 5.1 Register Bit Configurations
- 178
  Register Descriptions
- 179
  Exception Handling Functions
  - 179
    Exception Handling Flow
  - 179
    Exception Handling Vector Addresses
- 180
  Exception Types and Priorities
- 180
  Figure 21.3 H-UDI Reset
- 180
  Table 5.2 Exceptions
- 182
  Exception Flow
  - 183
    Exception Source Acceptance
  - 183
    Figure 5.2 Instruction Execution and Exception Handling
  - 184
    Figure 5.3 Example of General Exception Acceptance Order
  - 185
    Exception Requests and BL Bit
  - 185
    Return From Exception Handling
- 185
  Description of Exceptions
  - 186
    Resets
  - 187
    Table 5.3 Types of Reset
  - 191
    General Exceptions
  - 205
    Interrupts
  - 208
    Priority Order With Multiple Exceptions
- 209
  Usage Notes
- 210
  Restrictions
- 211
  Data Formats
  - 211
    Floating-Point Format
  - 211
    Figure 6.1 Format of Single-Precision Floating-Point Number
  - 212
    Figure 6.2 Format of Double-Precision Floating-Point Number
  - 212
    Table 6.1 Floating-Point Number Formats and Parameters
  - 213
    Non-Numbers (Nan)
  - 213
    Table 6.2 Floating-Point Ranges
  - 214
    Denormalized Numbers
  - 214
    Figure 6.3 Single-Precision Nan Bit Pattern
- 211
  Floating-Point Unit
- 211
  Overview
- 215
  Registers
  - 215
    Floating-Point Registers
  - 216
    Figure 6.4 Floating-Point Registers
  - 217
    Floating-Point Status/Control Register (FPSCR)
  - 218
    Floating-Point Communication Register (FPUL)
- 218
  Rounding
- 219
  Floating-Point Exceptions
- 220
  Graphics Support Functions
  - 220
    Geometric Operation Instructions
  - 222
    Pair Single-Precision Data Transfer
- 223
  Execution Environment
- 223
  Instruction Set
- 225
  Addressing Modes
- 228
  Table 7.1 Addressing Modes and Effective Addresses
- 229
  Instruction Set
- 229
  Table 7.2 Notation Used in Instruction List
- 230
  Table 7.3 Fixed-Point Transfer Instructions
- 233
  Table 7.4 Arithmetic Operation Instructions
- 234
  Table 7.5 Logic Operation Instructions
- 235
  Table 7.6 Shift Instructions
- 236
  Table 7.7 Branch Instructions
- 237
  Table 7.8 System Control Instructions
- 239
  Table 7.9 Floating-Point Single-Precision Instructions
- 240
  Table 7.10 Floating-Point Double-Precision Instructions
- 240
  Table 7.11 Floating-Point Control Instructions
- 241
  Table 7.12 Floating-Point Graphics Acceleration Instructions
- 243
  Pipelines
- 243
  Pipelining
- 244
  Figure 8.1 Basic Pipelines
- 249
  Figure 8.2 Instruction Execution Patterns
- 250
  Parallel-Executability
- 250
  Table 8.1 Instruction Groups
- 254
  Execution Cycles and Pipeline Stalling
- 254
  Table 8.2 Parallel-Executability
- 259
  Figure 8.3 Examples of Pipelined Execution
- 261
  Table 8.3 Execution Cycles
- 271
  Overview
  - 271
    Types of Power-Down Modes
  - 272
    Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
  - 273
    Register Configuration
  - 273
    Pin Configuration
  - 273
    Table 9.2 Power-Down Mode Registers
  - 273
    Table 9.3 Power-Down Mode Pins
- 271
  Power-Down Modes
- 274
  Register Descriptions
  - 274
    Standby Control Register (STBCR)
  - 276
    Peripheral Module Pin High Impedance Control
  - 276
    Peripheral Module Pin Pull-Up Control
  - 277
    Standby Control Register 2 (STBCR2)
  - 278
    Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
  - 279
    Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
- 280
  Deep Sleep Mode
  - 280
    Transition to Deep Sleep Mode
  - 281
    Exit From Deep Sleep Mode
- 280
  Sleep Mode
  - 280
    Transition to Sleep Mode
  - 280
    Exit From Sleep Mode
- 281
  Standby Mode
  - 281
    Transition to Standby Mode
  - 281
    Table 9.4 State of Registers in Standby Mode
  - 282
    Exit From Standby Mode
  - 282
    Clock Pause Function
- 283
  Module Standby Function
  - 283
    Transition to Module Standby Function
  - 284
    Exit From Module Standby Function
- 285
  Hardware Standby Mode (SH7750S, SH7750R Only)
  - 285
    Transition to Hardware Standby Mode
  - 285
    Exit From Hardware Standby Mode
  - 285
    Usage Notes
- 286
  STATUS Pin Change Timing
  - 287
    In Reset
  - 287
    Figure 9.1 STATUS Output in Power-On Reset
  - 287
    Figure 9.2 STATUS Output in Manual Reset
  - 288
    In Exit From Standby Mode
  - 288
    Figure 9.3 STATUS Output in Standby → Interrupt Sequence
  - 288
    Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence
  - 289
    Figure 9.5 STATUS Output in Standby → Manual Reset Sequence
  - 290
    In Exit From Sleep Mode
  - 290
    Figure 9.6 STATUS Output in Sleep → Interrupt Sequence
  - 290
    Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence
  - 291
    Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence
  - 292
    In Exit From Deep Sleep Mode
  - 292
    Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
  - 292
    Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
  - 293
    Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence
  - 294
    Hardware Standby Mode Timing (SH7750S, SH7750R Only)
  - 294
    Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
  - 295
    Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
  - 296
    Figure 9.14 Timing When Power Other Than VDD-RTC Is Off
  - 296
    Figure 9.15 Timing When VDD-RTC Power Is Off → On
- 297
  Overview
  - 297
    Features
- 297
  Section 10 Clock Oscillation Circuits
- 299
  Overview of CPG
  - 299
    Block Diagram of CPG
  - 299
    Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
  - 300
    Figure 10.1 (2) Block Diagram of CPG (SH7750R)
  - 302
    CPG Pin Configuration
  - 302
    CPG Register Configuration
  - 302
    Table 10.1 CPG Pins
  - 302
    Table 10.2 CPG Register
- 303
  Clock Operating Modes
- 303
  Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
- 303
  Table 10.3 (2) Clock Operating Modes (SH7750R)
- 304
  CPG Register Description
  - 304
    Frequency Control Register (FRQCR)
  - 304
    Table 10.4 FRQCR Settings and Internal Clock Frequencies
- 307
  Changing the Frequency
  - 307
    Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
  - 307
    Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
  - 308
    Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
  - 308
    Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
  - 308
    Changing CPU or Peripheral Module Clock Division Ratio
- 308
  Output Clock Control
- 309
  Overview of Watchdog Timer
  - 309
    Block Diagram
  - 309
    Figure 10.2 Block Diagram of WDT
  - 310
    Register Configuration
- 310
  WDT Register Descriptions
  - 310
    Watchdog Timer Counter (WTCNT)
  - 310
    Table 10.5 WDT Registers
  - 311
    Watchdog Timer Control/Status Register (WTCSR)
  - 313
    Notes On Register Access
- 313
  Using the WDT
  - 313
    Standby Clearing Procedure
  - 313
    Figure 10.3 Writing to WTCNT and WTCSR
  - 314
    Frequency Changing Procedure
  - 314
    Using Watchdog Timer Mode
  - 315
    Using Interval Timer Mode
- 315
  Figure 10.4 Points for Attention When Using Crystal Resonator
- 315
  Notes On Board Design
- 316
  Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
- 317
  Overview
  - 317
    Features
  - 318
    Block Diagram
  - 318
    Figure 11.1 Block Diagram of RTC
  - 319
    Pin Configuration
  - 319
    Register Configuration
  - 319
    Table 11.1 RTC Pins
  - 319
    Table 11.2 RTC Registers
- 317
  Section 11 Realtime Clock (RTC)
- 321
  Register Descriptions
  - 321
    64 Hz Counter (R64CNT)
  - 321
    Second Counter (RSECCNT)
  - 322
    Minute Counter (RMINCNT)
  - 322
    Hour Counter (RHRCNT)
  - 323
    Day-Of-Week Counter (RWKCNT)
  - 324
    Day Counter (RDAYCNT)
  - 324
    Month Counter (RMONCNT)
  - 325
    Year Counter (RYRCNT)
  - 326
    Second Alarm Register (RSECAR)
  - 326
    Minute Alarm Register (RMINAR)
  - 327
    Hour Alarm Register (RHRAR)
  - 327
    Day-Of-Week Alarm Register (RWKAR)
  - 328
    Day Alarm Register (RDAYAR)
  - 329
    Month Alarm Register (RMONAR)
  - 329
    RTC Control Register 1 (RCR1)
  - 331
    RTC Control Register 2 (RCR2)
  - 333
    RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)
    - 333
      (SH7750R Only)
- 335
  Operation
  - 335
    Time Setting Procedures
  - 335
    Figure 11.2 Examples of Time Setting Procedures
  - 336
    Time Reading Procedures
  - 337
    Figure 11.3 Examples of Time Reading Procedures
  - 338
    Alarm Function
  - 338
    Figure 11.4 Example of Use of Alarm Function
- 339
  Interrupts
- 339
  Usage Notes
  - 339
    Register Initialization
  - 339
    Carry Flag and Interrupt Flag in Standby Mode
  - 339
    Crystal Oscillator Circuit
  - 339
    Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)
  - 340
    Figure 11.5 Example of Crystal Oscillator Circuit Connection
- 341
  Overview
  - 341
    Features
  - 342
    Block Diagram
  - 342
    Pin Configuration
  - 342
    Figure 12.1 Block Diagram of TMU
  - 342
    Table 12.1 TMU Pins
  - 343
    Register Configuration
  - 343
    Table 12.2 TMU Registers
- 341
  Section 12 Timer Unit (TMU)
- 345
  Register Descriptions
  - 345
    Timer Output Control Register (TOCR)
  - 346
    Timer Start Register (TSTR)
  - 347
    Timer Start Register 2 (TSTR2) (SH7750R Only)
  - 348
    Timer Constant Registers (TCOR)
  - 348
    Timer Counters (TCNT)
  - 349
    Timer Control Registers (TCR)
  - 353
    Input Capture Register (TCPR2)
- 354
  Operation
  - 354
    Counter Operation
  - 355
    Figure 12.2 Example of Count Operation Setting Procedure
  - 355
    Figure 12.3 TCNT Auto-Reload Operation
  - 356
    Figure 12.4 Count Timing When Operating On Internal Clock
  - 356
    Figure 12.5 Count Timing When Operating On External Clock
  - 357
    Input Capture Function
  - 357
    Figure 12.6 Count Timing When Operating On On-Chip RTC Output Clock
- 358
  Figure 12.7 Operation Timing When Using Input Capture Function
- 358
  Interrupts
- 359
  Usage Notes
  - 359
    Register Writes
  - 359
    TCNT Register Reads
  - 359
    Resetting the RTC Frequency Divider
  - 359
    External Clock Frequency
  - 359
    Table 12.3 TMU Interrupt Sources
- 361
  Overview
  - 361
    Features
  - 363
    Block Diagram
  - 363
    Figure 13.1 Block Diagram of BSC
  - 364
    Pin Configuration
  - 364
    Table 13.1 BSC Pins
  - 368
    Register Configuration
  - 368
    Table 13.2 BSC Registers
  - 369
    Overview of Areas
  - 369
    Figure 13.2 Correspondence Between Virtual Address Space and External Memory Space
  - 370
    Table 13.3 External Memory Space Map
  - 371
    Figure 13.3 External Memory Space Allocation
  - 372
    PCMCIA Support
  - 372
    Table 13.4 PCMCIA Interface Features
  - 373
    Table 13.5 PCMCIA Support Interfaces
- 361
  Section 13 Bus State Controller (BSC)
- 376
  Register Descriptions
  - 376
    Bus Control Register 1 (BCR1)
  - 385
    Bus Control Register 2 (BCR2)
  - 387
    Bus Control Register 3 (BCR3) (SH7750R Only)
  - 388
    Bus Control Register 4 (BCR4) (SH7750R Only)
  - 388
    Figure 13.4 Example of RDY Sampling Timing at Which BCR4 Is Set (Two Wait Cycles Are Inserted By WCR2)
  - 390
    Wait Control Register 1 (WCR1)
  - 393
    Wait Control Register 2 (WCR2)
  - 400
    Table 13.6 MPX Interface Is Selected (Areas 0 to 6)
  - 401
    Wait Control Register 3 (WCR3)
  - 402
    Memory Control Register (MCR)
  - 409
    PCMCIA Control Register (PCR)
  - 412
    Synchronous DRAM Mode Register (SDMR)
  - 414
    Refresh Timer Control/Status Register (RTCSR)
  - 417
    Refresh Timer Counter (RTCNT)
  - 418
    Refresh Time Constant Register (RTCOR)
  - 419
    Refresh Count Register (RFCR)
  - 419
    13.2.15 Notes On Accessing Refresh Control Registers
- 420
  Operation
  - 420
    Endian/Access Size and Data Alignment
  - 420
    Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
  - 422
    Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment
  - 423
    Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment
  - 424
    Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
  - 425
    Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
  - 426
    Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
  - 427
    Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment
  - 428
    Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment