Download Print this page
   
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table of Contents
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990

Advertisement

Hitachi SuperH RISC engine
SH7750 Series
SH7750, SH7750S, SH7750R
Hardware Manual
ADE-602-124E
Rev. 6.0
7/10/2002
Hitachi, Ltd.

Advertisement

   Also See for Hitachi SH7750

   Related Manuals for Hitachi SH7750

   Summary of Contents for Hitachi SH7750

  • Page 1

    Hitachi SuperH RISC engine SH7750 Series SH7750, SH7750S, SH7750R Hardware Manual ADE-602-124E Rev. 6.0 7/10/2002 Hitachi, Ltd.

  • Page 2

    Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

  • Page 3

    SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and smart card interface.

  • Page 4

    • User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Hitachi Embedded Workshop User’s Manual ADE-702-201 Rev. 6.0, 07/02, page iv of I...

  • Page 5

    List of Items Revised or Added for This Version Section Page Item Description 1.1 SH7750 Series (SH7750, Description amended SH7750S, SH7750R) and added Features 4 to 8 Table 1.1 SH7750 Series Description added for Features LSI, and description and Note added for...

  • Page 6

    Description changed 3.3.7 Address Space Note added Identifier (ASID) 4.1.1 Features Completely revised Table 4.1 Cache Features Completely revised (SH7750, SH7750S) Table 4.2 Cache Features Newly added (SH7750R) Table 4.3 Features of Store Description added Queues 4.2 Register Descriptions Figure 4.1 Cache and Store...

  • Page 7

    Section Page Item Description 5.6.3 Interrupts (3) Peripheral Module Description changed Interrupts 7.3 Instruction Set Table 7.7 Branch Instructions Description added 8.3 Execution Cycles and 204 to Description amended Pipeline Stalling 9.1.1 Types of Power-Down Note changed Modes Table 9.1 Status of CPU and Hardware standby Peripheral Modules in Power- (SH7750S, SH7750R)

  • Page 8

    Figures changed Mode Timing (SH7750S, Notes added SH7750R Only) 10.2.1 Block Diagram of Figure 10.1 (1) Block Amended Diagram of CPG (SH7750, SH7750S) Figure 10.1 (2) Block Newly added Diagram of CPG (SH7750R) 10.2.2 CPG Pin Table 10.1 CPG Pins...

  • Page 9

    Section Page Item Description 11.2.2 Second Counter Description amended (RSECCNT) 11.2.17 RTC Control Newly added Register 3 (RCR3) and Year- Alarm Register (RYRAR) (SH7750R Only) 11.3.3 Alarm Function Description added 11.5.2 Carry Flag and Added Interrupt Flag in Standby Mode 11.5.3 Crystal Oscillator Figure 11.5 Example of Note amended...

  • Page 10

    Section Page Item Description 13.1.4 Register Configuration 318 Table 13.2 BSC Registers Bus control register 3 and 4 added to table, and Note added 64 * 13.1.5 Overview of Areas Table 13.3 External Memory added to Area 0, 5, Space Map 6 Settable Bus Widths, and Note 7 added Space Divisions...

  • Page 11

    Section Page Item Description 13.2.8 Memory Control Bits 15 to 13—Write Description added Register (MCR) Precharge Delay (TRWL2– TRWL0) For Synchronous DRAM AMX6 description and Interface Notes amended 13.2.10 Synchronous DRAM 362 to Description amended, Mode Register (SDMR) and Note added 13.3.1 Endian/Access Size Description amended and Data Alignment...

  • Page 12

    480, 481 Description added and amended 13.3.16 Notes on Usage Refresh, Bus Arbitration Description amended Synchronous DRAM Mode Newly added Register Setting (SH7750, SH7750R Only) 14.1 Overview Description added and amended 14.1.1 Features 489 to 491 Description amended 14.1.2 Block Diagram...

  • Page 13

    Section Page Item Description 14.2.1 DMA Source Address Description amended Registers 0–3 (SAR0–SAR3) 14.2.2 DMA Destination Description amended Address Registers 0–3 (DAR0–DAR3) 14.2.3 DMA Transfer Count Description amended Registers 0–3 (DMATCR0– DMATCR3) 14.2.4 DMA Channel Control Description of DDT Registers 0–3 (CHCR0– mode added CHCR3) 502, 503...

  • Page 14

    Section Page Item Description 14.6 Configuration of the Newly added DMAC (SH7750R) 14.7 Register Descriptions Newly added (SH7750R) 14.8 Operation (SH7750R) Added 14.9 Usage Notes Description amended Newly added 15.2.8 Serial Port Register Bit 7 Description amended (SCSPTR1) 16.1.2 Block Diagram Figure 16.1 Block Diagram Amended of SCIF...

  • Page 15

    Section Page Item Description 19.2.4 Interrupt Exception Description added Handling and Priority 759 to Table 19.5 Interrupt Description added to Exception Handling Sources table, Notes added and and Priority Order amended 19.3.1 Interrupt Priority Table 19.6 Interrupt Request SH7750R added to Registers A to D (IPRA–...

  • Page 16

    Section Page Item Description 21.1.3 Pin Configuration Table 21.1 H-UDI Pins Table amended and Note 3 added 21.1.4 Register Configuration 802 Table 21.2 H-UDI Registers Description added to table and Notes 3 and 4 added 21.2.1 Instruction Register [SH7750R] description (SDIR) added 21.2.4 Interrupt Source...

  • Page 17

    Section Page Item Description 22.2 DC Characteristics 836, 837 Table 22.13 Amended DC Characteristics (HD6417750SVF133) 838, 839 Table 22.14 Amended DC Characteristics (HD6417750SVBT133) 840, 841 Table 22.15 Amended DC Characteristics (HD6417750VF128) 22.3 AC Characteristics Table 22.17 Clock Timing Newly added (HD6417750RBP240) Table 22.18 Clock Timing Newly added...

  • Page 18

    Section Page Item Description 22.3.1 Clock and Control 850, 851 Table 22.28 Clock and Newly added Signal Timing Control Signal Timing (HD6417750RF200) 852, 853 Table 22.29 Clock and Newly added Control Signal Timing (HD6417750BP200M, HD6417750SBP200) 854, 855 Table 22.30 Clock and Amended Control Signal Timing (HD6417750SF200)

  • Page 19

    Section Page Item Description 22.3.4 Peripheral Module 924, 925 Table 22.36 Peripheral Table newly added Signal Timing Module Signal Timing (1) 900 to Figures 22.37 to 22.58, Titles amended 921, 923 Figure 22.60 Figure 22.62 RTC Oscillation Amended Settling Time at Power-On Figure 22.66(b) DBREQ/TR Newly added Input Timing and BAVL...

  • Page 20

    (256M: 4M × 16b × 4) × 2 (SH7750S and SH7750R only) Appendix H Power-On and 977 to Newly added Power-Off Procedures Appendix I Product Code Table I.1 SH7750 Series SH7750R added Lineup Product Code Lineup Rev. 6.0, 07/02, page xx of I...

  • Page 21: Table Of Contents

    Contents Section 1 Overview ......................SH7750 Series (SH7750, SH7750S, SH7750R) Features..........Block Diagram ........................Pin Arrangement ....................... 10 Pin Functions ........................13 1.4.1 Pin Functions (256-Pin BGA)................13 1.4.2 Pin Functions (208-Pin QFP)................23 1.4.3 Pin Functions (264-Pin CSP) ................31...

  • Page 22

    3.4.1 Unified TLB (UTLB) Configuration ..............71 3.4.2 Instruction TLB (ITLB) Configuration..............75 3.4.3 Address Translation Method................75 MMU Functions........................ 78 3.5.1 MMU Hardware Management ................78 3.5.2 MMU Software Management ................78 3.5.3 MMU Instruction (LDTLB)................. 78 3.5.4 Hardware ITLB Miss Handling ................79 3.5.5 Avoiding Synonym Problems ................

  • Page 23

    4.4.3 IC Index Mode ..................... 111 Memory-Mapped Cache Configuration (SH7750, SH7750S) .......... 112 4.5.1 IC Address Array ....................112 4.5.2 IC Data Array....................... 113 4.5.3 OC Address Array ....................114 4.5.4 OC Data Array ..................... 115 Memory-Mapped Cache Configuration (SH7750R)............116 4.6.1...

  • Page 24

    Section 6 Floating-Point Unit ..................161 Overview........................... 161 Data Formats........................161 6.2.1 Floating-Point Format..................161 6.2.2 Non-Numbers (NaN) ................... 163 6.2.3 Denormalized Numbers ..................164 Registers..........................165 6.3.1 Floating-Point Registers..................165 6.3.2 Floating-Point Status/Control Register (FPSCR)..........167 6.3.3 Floating-Point Communication Register (FPUL) ..........168 Rounding...........................

  • Page 25: Table Of Contents

    9.4.2 Exit from Deep Sleep Mode ................231 Standby Mode ........................231 9.5.1 Transition to Standby Mode................. 231 9.5.2 Exit from Standby Mode..................232 9.5.3 Clock Pause Function ..................232 Module Standby Function....................233 9.6.1 Transition to Module Standby Function .............. 233 9.6.2 Exit from Module Standby Function ..............

  • Page 26

    10.9 Using the WDT ......................... 263 10.9.1 Standby Clearing Procedure ................263 10.9.2 Frequency Changing Procedure ................264 10.9.3 Using Watchdog Timer Mode ................264 10.9.4 Using Interval Timer Mode ................. 265 10.10 Notes on Board Design ..................... 265 Section 11 Realtime Clock (RTC) ..................

  • Page 27

    Section 12 Timer Unit (TMU) ..................291 12.1 Overview........................... 291 12.1.1 Features........................ 291 12.1.2 Block Diagram..................... 292 12.1.3 Pin Configuration....................292 12.1.4 Register Configuration..................293 12.2 Register Descriptions ......................295 12.2.1 Timer Output Control Register (TOCR) .............. 295 12.2.2 Timer Start Register (TSTR)................296 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) ..........

  • Page 28

    Section 14 Direct Memory Access Controller (DMAC) .......... 489 14.1 Overview........................... 489 14.1.1 Features........................ 489 14.1.2 Block Diagram (SH7750, SH7750S) ..............492 14.1.3 Pin Configuration (SH7750, SH7750S)............... 493 14.1.4 Register Configuration (SH7750, SH7750S)............494 14.2 Register Descriptions (SH7750, SH7750S) ..............496 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ..........

  • Page 29

    14.4.1 Examples of Transfer between External Memory and an External Device with DACK ......................544 14.5 On-Demand Data Transfer Mode (DDT Mode) ............... 545 14.5.1 Operation ......................545 14.5.2 Pins in DDT Mode....................547 14.5.3 Transfer Request Acceptance on Each Channel ..........550 14.5.4 Notes on Use of DDT Module ................

  • Page 30

    15.3.2 Operation in Asynchronous Mode ............... 623 15.3.3 Multiprocessor Communication Function ............634 15.3.4 Operation in Synchronous Mode ................. 642 15.4 SCI Interrupt Sources and DMAC ..................651 15.5 Usage Notes ........................652 Section 16 Serial Communication Interface with FIFO (SCIF) ......

  • Page 31

    17.3.1 Overview......................710 17.3.2 Pin Connections ....................711 17.3.3 Data Format ......................712 17.3.4 Register Settings ....................713 17.3.5 Clock........................715 17.3.6 Data Transmit/Receive Operations ..............718 17.4 Usage Notes ........................725 Section 18 I/O Ports ......................731 18.1 Overview........................... 731 18.1.1 Features........................

  • Page 32

    20.6.1 Transition to User Break Controller Stopped State..........797 20.6.2 Cancelling the User Break Controller Stopped State ........... 797 20.6.3 Examples of Stopping and Restarting the User Break Controller......798 Section 21 Hitachi User Debug Interface (H-UDI) ........... 799 21.1 Overview........................... 799 21.1.1 Features........................

  • Page 33: Table Of Contents

    21.1.2 Block Diagram..................... 799 21.1.3 Pin Configuration....................801 21.1.4 Register Configuration..................802 21.2 Register Descriptions ......................803 21.2.1 Instruction Register (SDIR) ................. 803 21.2.2 Data Register (SDDR) ..................805 21.2.3 Bypass Register (SDBPR) ................... 805 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only).......... 806 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) ..........

  • Page 34

    Product Code Lineup ................. 979 Index ............................981 Figures Figure 1.1 Block Diagram of SH7750 Series Functions ........... Figure 1.2 Pin Arrangement (256-Pin BGA) ..............10 Figure 1.3 Pin Arrangement (208-Pin QFP)..............11 Figure 1.4 Pin Arrangement (264-Pin CSP)..............12 Figure 2.1...

  • Page 35

    Timing When Power Other than VDD-RTC is Off ......... 246 Timing When VDD-RTC Power is Off → On ..........246 Figure 9.15 Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) ..........249 Figure 10.1 (2) Block Diagram of CPG (SH7750R)..............250 Figure 10.2 Block Diagram of WDT...................

  • Page 36

    Figure 11.4 Example of Use of Alarm Function ..............288 Figure 11.5 Example of Crystal Oscillator Circuit Connection .......... 290 Figure 12.1 Block Diagram of TMU................... 292 Figure 12.2 Example of Count Operation Setting Procedure ..........305 Figure 12.3 TCNT Auto-Reload Operation................. 305 Figure 12.4 Count Timing when Operating on Internal Clock..........

  • Page 37

    Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) ..414 Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) ..415 Figure 13.28 Basic Timing for Synchronous DRAM Burst Read......... 417 Figure 13.29 Basic Timing for Synchronous DRAM Single Read ........

  • Page 38

    Figure 13.61 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ................461 Figure 13.62 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ................

  • Page 39

    Figure 14.1 Block Diagram of DMAC................492 Figure 14.2 DMAC Transfer Flowchart................511 Figure 14.3 Round Robin Mode..................516 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode ......517 Figure 14.5 Data Flow in Single Address Mode ..............519 Figure 14.6 DMA Transfer Timing in Single Address Mode ..........

  • Page 40

    Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ..553 Figure 14.28 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Figure 14.29 Block Transfer/Channel 0 On-Demand Data Transfer ........554 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Figure 14.30 Block Transfer/Channel 0 On-Demand Data Transfer ........

  • Page 41

    Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) ........584 Single Address Mode/Burst Mode/External Bus → External Device Figure 14.55 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer....... 589 Single Address Mode/Burst Mode/External Bus → External Device/ Figure 14.56 32-Byte Block Transfer/On-Demand Data Transfer on Channel 4....590 Figure 15.1 Block Diagram of SCI ..................

  • Page 42

    Figure 16.4 MD1/TxD2 Pin ....................683 Figure 16.5 MD2/RxD2 Pin ....................683 Figure 16.6 Sample SCIF Initialization Flowchart.............. 689 Figure 16.7 Sample Serial Transmission Flowchart............690 Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) ....................692 Figure 16.9 Example of Operation Using Modem Control (CTS2) ........

  • Page 43

    Figure 21.3 H-UDI Reset ....................811 Figure 22.1 EXTAL Clock Input Timing................862 Figure 22.2(1) CKIO Clock Output Timing ................862 Figure 22.2(2) CKIO Clock Output Timing ................862 Figure 22.3 Power-On Oscillation Settling Time..............863 Standby Return Oscillation Settling Time (Return by RESET)....... 863 Figure 22.4 Figure 22.5 Power-On Oscillation Settling Time..............

  • Page 44

    Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) ..892 Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)...................

  • Page 45

    Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) ............... 912 Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) ............... 913 Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)......914 Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait...

  • Page 46

    Output Load Circuit ..................934 Figure 22.73 Load Capacitance vs. Delay Time ..............935 Figure B.1 Package Dimensions (256-Pin BGA) (SH7750 and SH7750S) ....... 943 Figure B.2 Package Dimensions (256-Pin BGA) (SH7750R Only) ........944 Figure B.3 Package Dimensions (208-Pin QFP)..............945 Figure B.4...

  • Page 47

    Table 10.1 CPG Pins......................252 Table 10.2 CPG Register ..................... 252 Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) ........... 253 Table 10.3 (2) Clock Operating Modes (SH7750R)..............253 Table 10.4 FRQCR Settings and Internal Clock Frequencies..........254 Table 10.5 WDT Registers ....................

  • Page 48

    Table 14.2 DMAC Pins in DDT Mode ................494 Table 14.3 DMAC Registers....................494 Table 14.4 Selecting External Request Mode with RS Bits..........513 Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits....514 Table 14.6 Supported DMA Transfers................. 518 Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode..

  • Page 49

    Table 19.2 INTC Registers ....................753 IRL3–IRL0 Pins and Interrupt Levels ............... 756 Table 19.3 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1) ....757 Table 19.4 Table 19.5 Interrupt Exception Handling Sources and Priority Order......... 759 Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers........

  • Page 50

    Peripheral Module Signal Timing (3) ..............928 Table A.1 Address List ....................... 937 Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State ...... 951 Table I.1 SH7750 Series Product Code Lineup..............979 Rev. 6.0, 07/02, page l of I...

  • Page 51

    16-kbyte data cache. The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.

  • Page 52

    Table 1.1 SH7750 Series Features (cont) Item Features • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers •...

  • Page 53

    Table 1.1 SH7750 Series Features (cont) Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero •...

  • Page 54

    • Clock pulse Choice of main clock: generator (CPG)  SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL  SH7750R: 1, 6, or 12 times EXTAL • Clock modes:  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ...

  • Page 55

     16 kbytes, 2-way set associative  256 entries/way, 32-byte block length  Cache-double-mode (16-kbyte cache)  Index mode  SH7750/SH7750S-compatible mode (8 kbytes, direct mapping) • Operand cache (OC)  32 kbytes, 2-way set associative  512 entries/way, 32-byte block length ...

  • Page 56

    Table 1.1 SH7750 Series Features (cont) Item Features • Interrupt controller Five independent external interrupts: NMI, IRL3 to IRL0 (INTC) • 15-level encoded external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module •...

  • Page 57

    Table 1.1 SH7750 Series Features (cont) Item Features • Direct memory Physical address DMA controller: access controller  SH7750, SH7750S: 4-channel (DMAC)  SH7750R: 8-channel • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes • Address modes: ...

  • Page 58

    Table 1.1 SH7750 Series Features (cont) Item Features Product lineup Abbre- Voltage Operating viation (Internal) Frequency Model No. Package SH7750 1.95 V 200 MHz HD6417750BP200M 256-pin BGA 1.8 V 167 MHz HD6417750F167 208-pin QFP HD6417750F167I 1.5 V 128 MHz HD6417750VF128 SH7750S 1.95 V...

  • Page 59

    Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. Lower 32-bit data Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data BSC: Bus state controller...

  • Page 60: Pin Arrangement

    VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.2 Pin Arrangement (256-Pin BGA)

  • Page 61

    VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.3 Pin Arrangement (208-Pin QFP)

  • Page 62

    VSS-CPG XTAL EXTAL VDD-CPG VDDQ VDDQ TCLK VSS-RTC XTAL2 EXTAL2 VDD-PLL2 STATUS0 DACK0 VDDQ MD7/TXD VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/ VDDQ VDDQ VDD-RTC MD1/TXD2 NMI VSSQ MD5/ MD8/ VSSQ VDDQ VDDQ MD4/ VSSQ VSSQ SCK2 MD2/RXD2 VSSQ VDDQ STATUS1 DACK1 VSSQ VDDQ...

  • Page 63: Pin Functions, Pin Functions (256-pin Bga)

    Pin Functions 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bust start...

  • Page 64

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data/port (Port) (Port)

  • Page 65

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX BACK/ BSREQ acknowledge/ bus request BREQ/ BSACK request/bus acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) WE5/CAS5/ CAS5 D47–D40...

  • Page 66

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Address Address Address CKIO Clock output CKIO VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) CKIO *...

  • Page 67

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 115 W16 RD/WR Read/write RD/WR RD/WR RD/WR RD/WR WE2/CAS2/ CAS2 ICIORD 116 Y17 D23–D16 DQM2 DQM2/ select signal ICIORD WE3/CAS3/ CAS3 ICIOWR 117 W17 D31–D24 DQM3 DQM3/...

  • Page 68

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 142 R20 Data 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 Data 146 P20 Data 147 N19 Data...

  • Page 69

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 174 E19 Data ACCSIZE2 175 F18 VDDQ Power IO VDD (3.3 V) 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 E18 RD/WR2 RD/WR...

  • Page 70

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 197 C15 VDDQ Power IO VDD (3.3 V) 198 D15 VSSQ Power IO GND (0 V) 199 B15 MD7/TXD Mode/SCI data output MRESET SCK2 200 A16 SCK2/ SCIF clock/...

  • Page 71

    Table 1.2 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 225 D8 Address 226 A8 STATUS0 Status 227 B8 STATUS1 Status IOIS16 228 A7 MD6/ Mode/IOIS16 IOIS16 (PCMCIA) 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power IO GND (0 V)

  • Page 72

    7. NC pins must be left completely open, and not connected to a power supply, GND, etc. * 1 CKIO2 is not connected to PLL2. * 2 Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev. 6.0, 07/02, page 22 of 986...

  • Page 73: Pin Functions (208-pin Qfp)

    1.4.2 Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bust start (BS) (BS)

  • Page 74

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data Data Data Data Data Data Power Internal VDD (1.8 V) Power Internal GND (0 V) Data...

  • Page 75

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX WE4/CAS4/ CAS4 D39–D32 select DQM4 DQM4 signal WE1/CAS1/ CAS1 D15–D8 select DQM1 DQM1 signal WE0/CAS0/ CAS0 D7–D0 select DQM0 DQM0 signal Address Address Address Power Internal VDD Power...

  • Page 76

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND (0 V) Chip select 3 (CS3) Chip select 2 (CS2) Power Internal VDD Power Internal GND (0 V) RD/CASS/ FRAME Read/CAS/ FRAME FRAME...

  • Page 77

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND (0 V) Data Data Power Internal VDD Power Internal GND (0 V) Data Data Data Data Data Data VDDQ Power IO VDD (3.3 V) VSSQ Power...

  • Page 78

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) Data ACCSIZE2 VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) MD0/SCK Mode/SCI clock MD1/TXD2 Mode SCIF data TXD2 TXD2...

  • Page 79

    Table 1.3 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX MRESET SCK2 SCK2/ SCIF clock/ SCK2 SCK2 SCK2 SCK2 MRESET manual reset Power Internal VDD Power Internal GND (0 V) Address Address Address Address Address Address VDDQ...

  • Page 80

    7. The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package. 8. For a QFP package, the maximum operating frequency of the external bus is 84 MHz. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev. 6.0, 07/02, page 30 of 986...

  • Page 81: Pin Functions (264-pin Csp)

    1.4.3 Pin Functions (264-Pin CSP) Table 1.4 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bus start (BS) (BS)

  • Page 82

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND (0 V) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port)

  • Page 83

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX BREQ/ Bus request/bus BSACK acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) WE5/CAS5/ CAS5 D47–D40 select DQM5 DQM5...

  • Page 84

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Address CKIO Clock output CKIO VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) CKIO2 CKIO* CKIO M10 A6 Address U10 A5 Address N10 A4 Address...

  • Page 85

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 116 R14 WE6/CAS6/ CAS6 D55–D48 select DQM6 DQM6 signal 117 U14 VDDQ Power IO VDD (3.3 V) 118 U17 VSSQ Power IO GND (0 V) 119 U15 WE7/CAS7/ CAS7 D63–D56 select...

  • Page 86

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 145 K15 Data 146 K14 Data 147 K17 VDDQ Power IO VDD (3.3 V) 148 K13 VSSQ Power IO GND (0 V) 149 K16 Data 150 K12 Data...

  • Page 87

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 176 F16 MD0/SCK Mode/SCI1 clock 177 C15 MD1/TXD2 I/O Mode/SCIF TXD2 TXD2 TXD2 TXD2 TXD2 data output 178 E15 MD2/RXD2 I Mode/SCIF RXD2 RXD2 RXD2 RXD2 RXD2...

  • Page 88

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 198 D11 VSS Power Internal GND (0 V) 199 C11 A18 Address 200 F12 Address 201 B11 VDDQ Power IO VDD (3.3 V) 202 E11 VSSQ Power IO GND (0 V) 203 A11...

  • Page 89

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX ASEBRK/ 227 E6 Pin break/ BRKACK acknowledge (H-UDI 228 A6 Data out (H-UDI) 229 D7 Power Internal VDD (1.5 V) 230 B7 Power Internal GND (0 V) 231 E5 Mode (H-UDI)

  • Page 90

    Table 1.4 Pin Functions (cont) Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 256 M7 NC-13 257 N2 NC-14 258 P2 NC-15 259 P16 NC-16 260 R17 NC-17 261 T4 NC-18 262 T14 NC-19 263 U3 NC-20 264 U4 NC-21 Input...

  • Page 91

    Section 2 Programming Model Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...

  • Page 92

    Processor Modes: The SH7750 Series has two processor modes, user mode and privileged mode. The SH7750 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be...

  • Page 93

    Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.

  • Page 94

    R0 _ BANK0 R0 _ BANK0 R0 _ BANK1 *1 *2 *1 *3 *1 *4 R1 _ BANK0 R1 _ BANK1 R1 _ BANK0 R2 _ BANK0 R2 _ BANK0 R2 _ BANK1 R3 _ BANK0 R3 _ BANK0 R3 _ BANK1 R4 _ BANK0 R4 _ BANK1 R4 _ BANK0...

  • Page 95

    R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7750 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.

  • Page 96

    SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...

  • Page 97

    2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).

  • Page 98

    • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10...

  • Page 99

    Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 16 15 14 —...

  • Page 100

    Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.

  • Page 101

    Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...

  • Page 102: Memory-mapped Registers

    When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.

  • Page 103: Data Format In Registers, Data Formats In Memory

    Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.

  • Page 104: Processor States

    Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. Processor States The SH7750 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state.

  • Page 105: Processor Modes

    From any state when From any state when = 0 and = 0 and Power-on reset state Manual reset state = 0, Reset state = 1, = 1, Exception-handling state Bus request Bus request clearance Interrupt Interrupt Exception End of exception Bus-released state interrupt transition...

  • Page 106

    Rev. 6.0, 07/02, page 56 of 986...

  • Page 107

    (translation lookaside buffer: TLB). The SH7750 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).

  • Page 108

    (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 Series is referred to as virtual address space, and the address space in physical memory as physical address space.

  • Page 109

    Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 6.0, 07/02, page 59 of 986...

  • Page 110

    3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Value * Address * Address * Name tion Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL...

  • Page 111

    Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.

  • Page 112

    CPU in the SH7750S and SH7750R with MMUCR.AT = 0, access is always performed using the values of the SA and TC bits in this register. In the SH7750, it is not possible to access a PCMCIA interface area with MMUCR.AT = 0. In the SH7750 Series, access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s CHCRn.SSAn,...

  • Page 113

    TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction.

  • Page 114

    3.3.1 Physical Address Space The SH7750 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3.

  • Page 115

    User mode Figure 3.3 Physical Address Space (MMUCR.AT = 0) In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the values of the SA and TC bits set in the PTEA register.

  • Page 116

    P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000...

  • Page 117

    3.3.2 External Memory Space The SH7750 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).

  • Page 118

    Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.

  • Page 119

    3.3.4 On-Chip RAM Space In the SH7750 Series, half of the instruction cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.

  • Page 120

    event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB.

  • Page 121: Tlb Functions

    TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB.

  • Page 122

    • 1-kbyte page Virtual address Physical address 10 9 10 9 Offset Offset • 4-kbyte page Virtual address Physical address 12 11 12 11 Offset Offset • 64-kbyte page Virtual address Physical address 16 15 16 15 Offset Offset • 1-Mbyte page Virtual address Physical address 20 19...

  • Page 123

    • SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset.

  • Page 124

    • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0.

  • Page 125

    3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.

  • Page 126

    Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...

  • Page 127

    Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...

  • Page 128

    A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.

  • Page 129

    3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.

  • Page 130

    This problem does not occur with the instruction TLB or instruction cache . In the SH7750 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.

  • Page 131

    MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.

  • Page 132

    3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below.

  • Page 133

    3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.

  • Page 134

    3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.

  • Page 135

    Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.

  • Page 136

    Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains...

  • Page 137

    Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.

  • Page 138

    3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.

  • Page 139

    3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.

  • Page 140

    3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.

  • Page 141

    In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].

  • Page 142

    3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.

  • Page 143

    3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.

  • Page 144

    Rev. 6.0, 07/02, page 94 of 986...

  • Page 145

    4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset. For high-speed writing to external memories, the SH7750 series supports 32 bytes × 2 of store queues (SQ). Table 4.3 lists the features of these SQs.

  • Page 146

    Table 4.3 Features of Store Queues Item Store Queues 2 × 32 bytes Capacity Addresses H'E000 0000 to H'E3FF FFFF Write Store instruction (1-cycle write) Write-back Prefetch instruction (PREF instruction) Access right MMU off: according to MMUCR.SQMD MMU on: according to individual page PR 4.1.2 Register Configuration Table 4.4 shows the cache control registers.

  • Page 147

    0 must be specified in a write; the read value is 0. Figure 4.1 Cache and Store Queue Control Registers (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S) IIX: IC index enable...

  • Page 148

    • EMODE: Double-sized cache mode bit In the SH7750R, this bit indicates whether the double-sized cache mode is used or not. This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while the cache is being used.

  • Page 149

    4.3.1 Configuration The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R’s operand cache is 2-way set-associative. Each way consists of 512 cache lines.

  • Page 150

    1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Write data Read data Hit signal Figure 4.2 Configuration of Operand Cache(SH7750, SH7750S) Rev. 6.0, 07/02, page 100 of 986...

  • Page 151

    Effective address 26 25 13 12 RAM area judgment Longword (LW) selection [12:5] [13] Entry selection Address array (way 0, way 1) Data array (way 0, way 1) Tag address 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits...

  • Page 152

    • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid.

  • Page 153

    4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2.

  • Page 154

    4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2.

  • Page 155

    4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.

  • Page 156

    RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In the SH7750/SH7750S-compatible mode of the SH7750R, the 8-kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area.

  • Page 157

    4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In the SH7750 Series, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual.

  • Page 158

    Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.

  • Page 159

    19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) Rev. 6.0, 07/02, page 109 of 986...

  • Page 160

    Effective address 13 12 11 10 [11:5] [12] Entry Longword (LW) selection selection Address array Data array (way 0, way 1) (way 0, way1) Tag address 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...

  • Page 161

    • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address (address: 12–5). When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware.

  • Page 162

    Memory-Mapped Cache Configuration (SH7750, SH7750S) To enable the IC and OC to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.

  • Page 163

    other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine.

  • Page 164

    2 1 0 Address field 1 1 1 1 0 0 0 1 Entry Data field Longword data : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area.

  • Page 165

    3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB.

  • Page 166

    Instruction fetches from these areas are not possible. For reserved bits, a write value of 0 should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S- compatible mode, the configuration of the SH7750R’s memory-mapped cache is the same as that of the SH7750 or SH7750S.

  • Page 167

    4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field.

  • Page 168

    5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry 10 9 Data field : Validity bit : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area.

  • Page 169

    2 1 0 Address field 1 1 1 1 0 0 0 1 Entry Data field Longword data : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area.

  • Page 170

    When a write is performed to a cache line for which the U bit and V bit are both 1, after write- back of that cache line, the tag, U bit, and V bit specified in the data field are written. 3.

  • Page 171

    The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field.

  • Page 172

    Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.

  • Page 173

    External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register.

  • Page 174

    Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the SH7750R, original SQ contents are guaranteed.

  • Page 175

    If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs.

  • Page 176

    Example 3: When an instruction that generates an exception does not branch using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ;...

  • Page 177

    SH7750 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.

  • Page 178

    Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.

  • Page 179

    Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.

  • Page 180

    Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...

  • Page 181

    Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...

  • Page 182

    Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H'600 H'640 type module DMTE1 H'660 interrupt DMTE2 H'680 (module/ source) DMTE3 H'6A0 DMTE4 H'780 DMTE5 H'7A0 DMTE6 H'7C0...

  • Page 183

    exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed.

  • Page 184

    Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...

  • Page 185

    5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000).

  • Page 186

    5.6.1 Resets (1) Power-On Reset • Sources:  SCK2 pin high level and RESET pin low level  When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. •...

  • Page 187

    (2) Manual Reset • Sources:  SCK2 pin low level and RESET pin low level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the WT/IT bit and RSTS bit are both set to 1 in WTCSR.

  • Page 188

    (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.

  • Page 189

    (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.

  • Page 190

    (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.

  • Page 191

    5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].

  • Page 192

    (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.

  • Page 193

    (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].

  • Page 194

    (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...

  • Page 195

    (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'0000 0100 •...

  • Page 196

    (6) Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ...

  • Page 197

    (7) Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].

  • Page 198

    (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.

  • Page 199

    (9) General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...

  • Page 200

    (10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ...

  • Page 201

    (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.

  • Page 202

    (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.

  • Page 203

    (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.

  • Page 204

    (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.

  • Page 205

    5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT.

  • Page 206

    (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 • Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.

  • Page 207

    (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). •...

  • Page 208

    5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.

  • Page 209

    If the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instruction PR register write operation (PC → PR operation performed in BSR, BSRF, JSR) is inhibited. Usage Notes 1. Return from exception handling a.

  • Page 210

    Restrictions 1. Restrictions on first instruction of exception handling routine • Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. • When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.

  • Page 211

    A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The SH7750 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...

  • Page 212

    52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...

  • Page 213

    Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...

  • Page 214

    EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 Series as operation results are as follows: • Single-precision qNaN: H'7FBFFFFF •...

  • Page 215

    Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...

  • Page 216

    FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...

  • Page 217

    6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...

  • Page 218

    When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.

  • Page 219

    0, but the corresponding bit in the flag field remains unchanged. • Enable/disable exception handling The SH7750 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input ...

  • Page 220

    When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.  Inexact exception (I): An inexact result is generated. Graphics Support Functions The SH7750 Series supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations.

  • Page 221

    In future version of SH series, the above error is guaranteed, but the same result as SH7750 is not guaranteed. FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes: • Inner product (m ≠ n): This operation is generally used for surface/rear surface determination for polygon surfaces.

  • Page 222

    In addition to the powerful new geometric operation instructions, the SH7750 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair single- precision data transfer instructions. • FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) •...

  • Page 223

    PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH7750 Series’ instruction set is implemented with 16-bit fixed- length instructions. The SH7750 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.

  • Page 224

    In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.

  • Page 225

    Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.

  • Page 226

    Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn +...

  • Page 227

    Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.

  • Page 228

    Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.

  • Page 229

    Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ←: Summary of Transfer direction operation...

  • Page 230

    Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension → Rn (disp × 4 + PC & H'FFFFFFFC MOV.L @(disp,PC),Rn 1101nnnndddddddd —...

  • Page 231

    Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L R0,@(disp,GBR) 11000010dddddddd —...

  • Page 232

    Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...

  • Page 233

    Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...

  • Page 234

    Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...

  • Page 235

    Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...

  • Page 236

    Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...

  • Page 237

    Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm → GBR Rm,GBR 0100mmmm00011110 —...

  • Page 238

    Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged — GBR →...

  • Page 239

    Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 — —...

  • Page 240

    Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...

  • Page 241

    Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — — (Rm) → XDn FMOV @Rm,XDn 1111nnn1mmmm1000 —...

  • Page 242

    Rev. 6.0, 07/02, page 192 of 986...

  • Page 243

    Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750 Series. Pipelines Figure 8.1 shows the basic pipelines.

  • Page 244

    1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...

  • Page 245

    1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.

  • Page 246

    10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.

  • Page 247

    19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.

  • Page 248

    31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.

  • Page 249

    40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle : Cannot overlap a stage of the same kind, except when two instructions are Notes: executed in parallel.

  • Page 250

    Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.

  • Page 251

    Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...

  • Page 252

    Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...

  • Page 253

    Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...

  • Page 254

    Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...

  • Page 255

    The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...

  • Page 256

    Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)).

  • Page 257

    (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...

  • Page 258

    (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.

  • Page 259

    (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.

  • Page 260

    (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...

  • Page 261

    Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data transfer EXTS.B Rm,Rn — — — instructions EXTS.W Rm,Rn — — — EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...

  • Page 262

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data transfer MOV.W R0,@(disp,Rn) — — — instructions MOV.L Rm,@(disp,Rn) — — — MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...

  • Page 263

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...

  • Page 264

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...

  • Page 265

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...

  • Page 266

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...

  • Page 267

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...

  • Page 268

    Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL —...

  • Page 269

    4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6.

  • Page 270

    Rev. 6.0, 07/02, page 220 of 986...

  • Page 271

    Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...

  • Page 272

    Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Refreshing • Interrupt Sleep SLEEP Operating Halted Held Operating Held • Reset instruction (registers executed...

  • Page 273

    9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Standby control STBCR H'00 H'FFC00004 H'1FC00004 register Standby control STBCR2 H'00 H'FFC00010 H'1FC00010 register 2...

  • Page 274

    Register Descriptions 9.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow. Bit: STBY MSTP4...

  • Page 275

    to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again. Bit 4: MSTP4 Description DMAC operates (Initial value) DMAC clock supply is stopped Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication...

  • Page 276

    9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. • Relevant Pins SCI related pins MD0/SCK MD1/TXD2 MD7/TXD MD8/RTS2 CTS2...

  • Page 277

    1 is written. These bits are always read as 0. Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0.

  • Page 278

    Bit 1 (SH7750S and SH7750R)—Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable. Bit 1: MSTP6 Description SQ operating...

  • Page 279

    Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to channels 3 and 4 of the timer unit (TMU). Bit 1: CSTP1 Description Peripheral clock is supplied to TMU channels 3 and 4 (Initial value) Peripheral clock supply to TMU channels 3 and 4 is stopped Bit 0...

  • Page 280

    Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.

  • Page 281: Standby Mode

    9.4.2 Exit from Deep Sleep Mode As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. Standby Mode 9.5.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode.

  • Page 282

    9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the RESET pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, IRL* , RTC, or GPIO* interrupt is detected, the WDT starts counting.

  • Page 283: Module Standby Function

    Module Standby Function 9.6.1 Transition to Module Standby Function Setting the MSTP6–MSTP0, CSTP1, and CSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.

  • Page 284

    Description CSTP1 * Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supplied to TMU channels 3 and 4 is stopped CSTP0 * INTC detects interrupts on TMU channels 3 and 4 INTC does not detect interrupts on TMU channels 3 and 4 MSTP6 * SQ operates Clock supplied to SQ is stopped...

  • Page 285: Hardware Standby Mode (sh7750s, Sh7750r Only)

    Hardware Standby Mode (SH7750S, SH7750R Only) 9.7.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1.

  • Page 286: Status Pin Change Timing

    STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows:...

  • Page 287

    9.8.1 In Reset Power-On Reset CKIO PLL stabilization time SCK2 Normal Reset Normal STATUS 0–30 Bcyc 0–5 Bcyc Figure 9.1 STATUS Output in Power-On Reset Manual Reset CKIO SCK2 Normal Reset Normal STATUS 0–30 Bcyc ≥ 0 Bcyc Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle.

  • Page 288

    9.8.2 In Exit from Standby Mode Standby → → → → Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count Normal Standby Normal STATUS Figure 9.3 STATUS Output in Standby → → → → Interrupt Sequence Standby → → → → Power-On Reset Oscillation stops Reset CKIO...

  • Page 289

    Standby → → → → Manual Reset Oscillation stops Reset CKIO SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: *1 When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time.

  • Page 290

    9.8.3 In Exit from Sleep Mode Sleep → → → → Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.6 STATUS Output in Sleep → → → → Interrupt Sequence Sleep → → → → Power-On Reset Reset CKIO SCK2 Normal Sleep...

  • Page 291

    Sleep → → → → Manual Reset Reset CKIO SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.8 STATUS Output in Sleep → → → → Manual Reset Sequence Rev.

  • Page 292

    9.8.4 In Exit from Deep Sleep Mode Deep Sleep → → → → Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep → → → → Interrupt Sequence Deep Sleep → → → → Power-On Reset Reset CKIO SCK2...

  • Page 293

    Deep Sleep → → → → Manual Reset Reset CKIO SCK2 Sleep Normal Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep → → → → Manual Reset Sequence Rev.

  • Page 294

    9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the RESET pin level low, the clock starts when the CA pin level is switched to high. CKIO SCK2 (High)

  • Page 295

    Interrupt request WDT overflow CKIO (High) SCK2 (High) Standby * Standby Normal STATUS 0–10 Bcyc WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) Rev. 6.0, 07/02, page 245 of 986...

  • Page 296

    SCK2 Min 0s Min 0s Max 50 µs Note: * V DD-CPG DD-PLL1 DD-PLL2 Figure 9.14 Timing When Power Other than VDD-RTC is Off DD-RTC Power-on oscillation setting time Min 0s SCK2 Note: * V DD-PLL1/2 DD-CPG Figure 9.15 Timing When VDD-RTC Power is Off → → → → On Rev.

  • Page 297

    Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed.

  • Page 298

    The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. • Can be switched between watchdog timer mode and interval timer mode •...

  • Page 299: Overview Of Cpg, Block Diagram Of Cpg

    10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1 (2) a block diagram of the CPG in the SH7750R. Oscillator circuit Frequency divider 2 ×...

  • Page 300

    Oscillator circuit Frequency divider 2 × 1 PLL circuit 1 × 1/2 × 6 × 1/3 × 12 CPU clock (Iø) × 1/4 cycle Icyc × 1/6 × 1/8 Crystal XTAL Peripheral module oscillator clock (Pø) cycle Pcyc EXTAL Bus clock (Bø) cycle Bcyc PLL circuit 2 ×...

  • Page 301

    PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6 with the SH7750 and SH7750S, and by 6 or 12 with the SH7750R. Starting and stopping is controlled by a frequency control register setting. Control is performed so that the internal clock rising edge phase matches the input clock rising edge phase.

  • Page 302

    10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins XTAL Output Connects crystal resonator (clock input pins) EXTAL Input Connects crystal resonator, or used as...

  • Page 303: Clock Operating Modes

    Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) External Frequency Pin Combination (vs.

  • Page 304: Cpg Register Description

    Table 10.4 FRQCR Settings and Internal Clock Frequencies Frequency Division Ratio FRQCR (Lower 9 Bits) CPU Clock Bus Clock Peripheral Module Clock H'008 H'00A H'00C H'011 H'013 H'01A H'01C H'023 H'02C H'05A H'05C H'063 H'06C H'0A3 H'0EC Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table. 10.4 CPG Register Description 10.4.1...

  • Page 305

    Bit: — — — — CKOEN PLL1EN PLL2EN IFC2 Initial value: — R/W: Bit: IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 Initial value: — — — — — — — — R/W: Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0. Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state.

  • Page 306

    Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 Bit 7: IFC1 Bit 6: IFC0 Description ×...

  • Page 307: Changing The Frequency

    10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below.

  • Page 308: Output Clock Control

    10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2.

  • Page 309: Overview Of Watchdog Timer

    10.7 Overview of Watchdog Timer 10.7.1 Block Diagram Figure 10.2 shows a block diagram of the WDT. Standby Standby Standby mode release control Frequency divider 2 ×1 clock Internal reset Frequency divider Reset request control Clock selection Clock selector Interrupt Interrupt Overflow request...

  • Page 310: Wdt Register Descriptions

    10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation Value P4 Address Address Access Size Watchdog timer WTCNT R/W* H'00 H'FFC00008...

  • Page 311

    10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the RESET pin. It retains its value in an internal reset due to WDT overflow.

  • Page 312

    Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description No overflow (Initial value) WTCNT has overflowed in watchdog timer mode Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode.

  • Page 313

    10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction.

  • Page 314

    4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 5. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 6.

  • Page 315

    CL1 = CL2 = 0–33 pF R = 0Ω EXTAL XTAL SH7750 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.

  • Page 316

    RCB1 = RCB2 = 10 CPB1 = CPB2 = 10 F RB = 10 CB = 10 F RCB2 VDD-PLL2 CPB2 SH7750 Series VSS-PLL2 VDD-CPG 3.3 V VSS-CPG Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Rev. 6.0, 07/02, page 266 of 986...

  • Page 317

    Section 11 Realtime Clock (RTC) 11.1 Overview The SH7750 Series includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.

  • Page 318

    11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC crystal RTC operation 32.768 kHz Prescaler oscillator control unit 128 Hz RCR1 RCR2 Counter unit RCR3 Interrupt R64CNT control unit RSECCNT RMINCNT RHRCNT RDAYCNT...

  • Page 319

    11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Clock input/clock output TCLK External clock input pin/input capture control input pin/RTC output pin...

  • Page 320

    Table 11.2 RTC Registers (cont) Initialization Abbrevia- Power-On Manual Standby Initial Area 7 Access Name tion Reset Reset Mode Value P4 Address Address Size Month RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter Year RYRCNT R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16...

  • Page 321

    11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.

  • Page 322

    11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.

  • Page 323

    11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.

  • Page 324

    11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.

  • Page 325

    Bit: — — — 0-month 1-month units unit Initial value: Undefined Undefined Undefined Undefined Undefined R/W: 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter.

  • Page 326

    11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

  • Page 327

    11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

  • Page 328

    Bit: — — — — Day of week code Initial value: Undefined Undefined Undefined R/W: Day-of-week code Day of week 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded day value counter, RDAYCNT.

  • Page 329

    11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.

  • Page 330

    Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.

  • Page 331

    Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description Alarm registers and counter values do not match (Initial value)

  • Page 332

    Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF Interrupt is generated at interval specified by bits PES2–PES0...

  • Page 333

    Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time.

  • Page 334

    Bits 6 to 0 of RCR3 are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0. RCR3 Bit: YENB — — — — — — — Initial value: R/W: RYRAR...

  • Page 335

    11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0 Reset frequency divider Set second/minute/hour/day/ In any order day-of-week/month/year Set RCR2.START to 1...

  • Page 336

    The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data.

  • Page 337

    Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Carry flag = 1? Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Set RCR1.CIE to 1 Enable carry interrupts...

  • Page 338

    11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Be sure to reset the flag as it may have been Clear alarm flag set during alarm time setting Set RCR1.AIE to 1 Enable alarm interrupts...

  • Page 339

    11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2–...

  • Page 340

    SH7750 Series EXTAL2 VDD-RTC XTAL2 VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value R (typ.

  • Page 341

    The SH7750 Series of microprocessors include an on-chip 32-bit timer unit (TMU). The TMU of the SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the SH7750R has five channels (channels 0 to 4).

  • Page 342

    12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. RESET, STBY, TUNE0,TUNE1 PCLK/4,16, 64 TUNI2 ICPI2 TCLK RTCCLK TUNI3, 4 etc. TCLK Prescaler control unit control unit To each To channels TOCR channel 0 to 2 TSTR TSTR2 Ch 0, 1 Ch 2...

  • Page 343

    12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Com- Timer TOCR R/W Ini- Ini- Held H'00 H’FFD80000 H'1FD80000 8...

  • Page 344

    Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Timer TCOR3 R/W Ini- Held Held H'FFFFFFFF H’FE100008 H'1E100008 32 constant tialized register 3 Timer TCNT3 R/W Ini- Held Held H'FFFFFFFF H’FE10000C H'1E10000C 32 counter 3...

  • Page 345

    12.2 Register Descriptions 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.

  • Page 346

    12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pφ).

  • Page 347

    12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3–4 timer counters (TSTR2) run or are stopped. TSTR2 is initialized to H'00 by a power-on reset and retains its value in standby mode. If standby mode is entered when the STR3 or STR4 bit is set to 1, counting is halted at the same time as the peripheral module clock is stopped.

  • Page 348

    12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode.

  • Page 349

    input clock is the external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in standby mode. 12.2.6 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for each channel. Each TCR selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT) underflow is set to 1.

  • Page 350

    2. Channel 2 TCR bit configuration Bit: — — — — — — ICPF Initial value: R/W: Bit: ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W: 3. TCR bit configuration for channels 3 and 4 (SH7750R only) Bit: —...

  • Page 351

    Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF Description TCNT has not underflowed (Initial value) [Clearing condition] When 0 is written to UNF TCNT has underflowed [Setting condition] When TCNT underflows* Note: * Writing 1 does not change the value. Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used.

  • Page 352

    Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. Bit 5: UNIE Description Interrupt due to underflow (TUNI) is not enabled (Initial value) Interrupt due to underflow (TUNI) is enabled Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input edge when an external clock is selected or the input capture function is used in channels 0 to 2.

  • Page 353

    12.2.7 Input Capture Register (TCPR2) TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the input capture control bits (ICPE) and clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2.

  • Page 354

    12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32- bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.

  • Page 355

    Operation selection Select count clock Underflow interrupt generation setting When input capture function is used Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.

  • Page 356

    TCNT Count Timing: • Operating on internal clock Any of five count clocks (Pφ/4, Pφ/16, Pφ/64, Pφ/256, or Pφ/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case.

  • Page 357

    • Operating on on-chip RTC output clock The on-chip RTC output clock can be selected as the timer clock in channels 0 to 2 by means of the TPSC2–TPSC0 bits in TCR. Figure 12.6 shows the timing in this case. RTC output clock N + 1 N –...

  • Page 358

    TCOR value set in TCNT TCNT value on underflow TCOR H'00000000 Time TCLK TCPR2 TCNT value set TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used).

  • Page 359

    Table 12.3 TMU Interrupt Sources Channel Interrupt Source Description Priority TUNI0 Underflow interrupt 0 High TUNI1 Underflow interrupt 1 TUNI2 Underflow interrupt 2 TICPI2 Input capture interrupt 2 TUNI3 Underflow interrupt 3 TUNI4 Underflow interrupt 4 Note: * SH7750R only 12.5 Usage Notes 12.5.1...

  • Page 360

    Rev. 6.0, 07/02, page 310 of 986...

  • Page 361

    The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7750 Series, and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system.

  • Page 362

     Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 • Synchronous DRAM interface  Row address/column address multiplexing according to synchronous DRAM capacity  Burst operation  Auto-refresh and self-refresh  Synchronous DRAM control signal timing can be controlled by register settings ...

  • Page 363

    13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 BCR1 – Area control unit – BCR2 BCR3 * BCR4 * – Memory control unit RFCR RTCNT Refresh Interrupt Comparator control unit controller RTCOR RTCSR...

  • Page 364

    13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25–A0 Address output Data bus D63–D52, Data input/output D31–D0 When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D60-D52 cannot be used and should be left open.

  • Page 365

    Table 13.1 BSC Pins (cont) Name Signals Description WE1/CAS1/ Data enable 1 When setting synchronous DRAM interface: DQM1 selection signal for D15–D8 When setting DRAM interface: CAS signal for D15–D8 When setting PCMCIA interface: write strobe signal When setting MPX interface: high-level output In other cases: write strobe signal for D15–D8 WE2/CAS2/ Data enable 2...

  • Page 366

    Table 13.1 BSC Pins (cont) Name Signals Description WE6/CAS6/ Data enable 6 When setting synchronous DRAM interface: DQM6 selection signal for D55–D48 When setting DRAM interface: CAS signal for D55–D48 When setting MPX interface: high-level output In other cases: write strobe signal for D55–D48 WE7/CAS7/ Data enable 7 When setting synchronous DRAM interface:...

  • Page 367

    Table 13.1 BSC Pins (cont) Name Signals Description Same signal as RD/CASS/FRAME Read/column address strobe/ This signal is used when the RD/CASS/FRAME cycle frame 2 signal load is heavy. Read/write 2 RD/WR2 Same signal as RD/WR This signal is used when the RD/WR signal load is heavy.

  • Page 368

    The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7750 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing.

  • Page 369

    With the SH7750 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (CS0–CS6, CE2A, CE2B) are output for each of these areas.

  • Page 370

    Table 13.3 External Memory Space Map External Connectable Settable Bus Area Addresses Size Memory Widths Access Size 8, 16, 32, 64 * H'00000000– 64 Mbytes SRAM 8, 16, 32, 64 * H'03FFFFFF bits, 8, 16, 32 * , 64 * Burst ROM 32 bytes 32, 64 *...

  • Page 371

    Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7750 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the RESET pin, using external pins.

  • Page 372

    Note: * SH7750R only 13.1.6 PCMCIA Support The SH7750 Series supports PCMCIA compliant interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1).

  • Page 373

    Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Ground Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...

  • Page 374

    Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data WP *...

  • Page 375

    Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Reserved Reserved — RESET Reset RESET Reset Output from port WAIT WAIT Wait request Wait request...

  • Page 376

    13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.

  • Page 377

    (MD6) is low, designating the area 0 as MPX interface Bits 28, 27, 26*, 23, 22, 16*, and 1—Reserved: These bits are always read as 0, and should only be written with 0. Note: * SH7750, SH7750S only. Rev. 6.0, 07/02, page 327 of 986...

  • Page 378

    Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected. Bit 26: DPUP Description Sets pullup resistance of data pins (D63 to D0) ON...

  • Page 379

    Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC Description Area 4 SRAM is set to normal mode (Initial value) Area 4 SRAM is set to byte control mode Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.

  • Page 380

    Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only): Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not performed until the end of the DMAC’s burst transfer.

  • Page 381

    Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored. Bit 13: A0BST2 Bit 12: A0BST1 Bit 11: A0BST0...

  • Page 382

    Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0...

  • Page 383

    Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0...

  • Page 384

    Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description Areas 2 and 3 are SRAM interface or MPX interface *...

  • Page 385

    13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode.

  • Page 386

    Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Description Bus width is 64 bits Bus width is 8 bits Bus width is 16 bits...

  • Page 387

    13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used. BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.

  • Page 388

    Bits 12 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0    Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is used. The burst-length setting is only valid when the bus width is 32 bits. Bit 0: SDBL Description Burst length is 8...

  • Page 389

    Bit: Bit name: — — — — — — — — Initial value: R/W: Bit: Bit name: — — — — — — — — Initial value: R/W: Bit: Bit name: — — — — — — — — Initial value: R/W: Bit: Bit name:...

  • Page 390

    In the SH7750 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision.

  • Page 391

    Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only be written with 0. Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2– DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the same device.

  • Page 392

    • Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address CPU DMA CPU DMA CPU DMA CPU DMA Cycle Output Output Read M (1) M (1) Write DMA read —...

  • Page 393

    13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access. This enables low-speed memory to be connected without using external circuitry.

  • Page 394

    Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle RDY Pin Bit 31: A6W2...

  • Page 395

    Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle RDY Pin Bit 25: A5W2...

  • Page 396

    Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description RDY Pin Bit 19: A4W2 Bit 18: A4W1...

  • Page 397

    • When DRAM or Synchronous DRAM Interface is Set* Description DRAM CAS Synchronous DRAM CAS Latency Cycles Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 Assertion Width Inhibited Inhibited Inhibited Notes: *1 External wait input is always ignored. *2 Inhibited in RAS down mode. Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2.

  • Page 398

    • When DRAM or Synchronous DRAM Interface is Set* Description DRAM CAS Synchronous DRAM CAS Latency Cycles Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Assertion Width Inhibited Inhibited Inhibited Notes: *1 External wait input is always ignored. *2 RAS down mode is prohibited. Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1.

  • Page 399

    Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle RDY Pin...

  • Page 400

    Table 13.6 MPX Interface is Selected (Areas 0 to 6) Description Inserted Wait States 1st Data 2nd Data RDY Pin AnW2 AnW1 AnW0 Read Write Onward Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled (n = 6 to 0) Rev. 6.0, 07/02, page 350 of 986...

  • Page 401

    13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry.

  • Page 402

    Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface. Bit 4n + 2: AnS0 Waits Inserted in Setup (Initial value)

  • Page 403

    on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the same values should be written to the other bits so that they remain unchanged. When using DRAM or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is completed.

  • Page 404

    Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. Bit 30: MRSET Description All-bank precharge (Initial value) Mode register setting Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled;...

  • Page 405

    Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is set, these bits specify the minimum number of cycles until RAS is asserted again after being negated. When the synchronous DRAM interface is set, these bits specify the minimum number of cycles until the next bank active command is output after precharging.

  • Page 406

    Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time 1 (Initial value) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Note: * Inhibited in RAS down mode. Bits 12 to 10—CAS-Before-RAS Refresh RAS RAS Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.

  • Page 407

    EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer Single Single Setting prohibited Setting prohibited Single/fast page* Fast page Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus. Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM.

  • Page 408

    Notes: *1 a[*]: Not an address pin but an external address *2 Can only be set in the SH7750R. *3 Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750). *4 For details on address multiplexing, refer to appendix F, Synchronous DRAM Address Multiplexing Tables.

  • Page 409

    Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS- before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR.

  • Page 410

    Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 15: A5PCW1 Bit 14: A5PCW0 Waits Inserted...

  • Page 411

    OE/WE WE Assertion Delay (A6TED2–A6TED0): These bits set the delay Bits 8 to 6—Address-OE time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0...

  • Page 412

    DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7750 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7750 Series, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.

  • Page 413

    For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written to the SDMR register. The range of value “X” is H'0000 to H'0FFC. Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0).

  • Page 414

    LMODE: RAS-CAS latency Burst length Wrap type (0: Sequential) LMODE 000: Reserved 000: Reserved 001: Reserved 001: 1 010: 4 010: 2 011: 8 011: 3 100: Reserved 100: Reserved 101: Reserved 101: Reserved 110: Reserved 110: Reserved 111: Reserved 111: Reserved Note: * SH7750R only.

  • Page 415

    Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF Description RTCNT and RTCOR values do not match (Initial value) [Clearing condition] When 0 is written to CMF RTCNT and RTCOR values match [Setting condition] When RTCNT = RTCOR*...

  • Page 416

    Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF Description RFCR has not overflowed the count limit indicated by LMTS (Initial value) [Clearing condition] When 0 is written to OVF...

  • Page 417

    13.2.12 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the RTCNT counter is cleared.

  • Page 418

    13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are constantly compared, and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0.

  • Page 419

    13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.

  • Page 420

    13.3.1 Endian/Access Size and Data Alignment The SH7750 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end.

  • Page 421

    Data Configuration Byte Data 7 to 0 Word Data 15 to 8 Data 7 to 0 Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Quadword Data Data Data Data Data Data Data Data 63 to 56...

  • Page 422

    Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte Data — — — — — — — 7–0 8n+1 — Data — — —...

  • Page 423

    Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Strobe Signals WE7, WE6, WE5, WE4, WE3, WE2, WE1, WE0, CAS7 CAS7, CAS7 CAS7 CAS6 CAS6, CAS6 CAS6 CAS5 CAS5 CAS5 CAS5, CAS4 CAS4 CAS4 CAS4, CAS3 CAS3 CAS3 CAS3, CAS2 CAS2,...

  • Page 424

    Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3, CAS3 CAS3 CAS2 CAS2, CAS2 CAS2 CAS1 CAS1, CAS1 CAS1 CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...

  • Page 425

    Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3, CAS3 CAS3 CAS2 CAS2, CAS2 CAS2 CAS1 CAS1 CAS1 CAS1, CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...

  • Page 426

    Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3, CAS3 CAS3 CAS2 CAS2, CAS2 CAS2 CAS1 CAS1, CAS1 CAS1 CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...

  • Page 427

    Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte — — — — — — — Data 7–0 8n+1 — — — — —...

  • Page 428

    Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Strobe Signals WE7, WE6, WE5, WE4, WE3, WE2, WE1, WE0, CAS7 CAS7 CAS7 CAS7, CAS6 CAS6, CAS6 CAS6 CAS5 CAS5, CAS5 CAS5 CAS4 CAS4, CAS4 CAS4 CAS3 CAS3 CAS3 CAS3, CAS2 CAS2...

  • Page 429

    Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3 CAS3 CAS3, CAS2 CAS2, CAS2 CAS2 CAS1 CAS1, CAS1 CAS1 CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3...

  • Page 430

    Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3 CAS3 CAS3, CAS2 CAS2, CAS2 CAS2 CAS1 CAS1, CAS1 CAS1 CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...

  • Page 431

    Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3 CAS3, CAS3 CAS3 CAS2 CAS2, CAS2 CAS2 CAS1 CAS1 CAS1 CAS1, CAS0 CAS0, CAS0 CAS0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...

  • Page 432

    13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3.

  • Page 433

    Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register.

  • Page 434

    When SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register.

  • Page 435

    Area 5: For area 5, external address bits A28 to A26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register.

  • Page 436

    Area 6: For area 6, external address bits A28 to A26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register.

  • Page 437

    13.3.3 SRAM Interface Basic Timing: The SRAM interface of the SH7750 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.

  • Page 438

    CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) SA: Single address DMA DA: Dual address DMA Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.6 Basic Timing of SRAM Interface Rev.

  • Page 439

    Figures 13.7, 13.8, 13.9, and 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. × 128k 8-bit SH7750 Series SRAM A19–A3 A16–A0 D63–D56 I/O7–I/O0 A16–A0 D55–D48 I/O7–I/O0 A16–A0 D47–D40 I/O7–I/O0 A16–A0 D39–D32 I/O7–I/O0 A16–A0 D31–D24 I/O7–I/O0...

  • Page 440

    128k × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 32-Bit Data Width SRAM Connection Rev. 6.0, 07/02, page 390 of 986...

  • Page 441

    128k × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.9 Example of 16-Bit Data Width SRAM Connection Rev. 6.0, 07/02, page 391 of 986...

  • Page 442

    128k × 8-bit SH7750 Series SRAM I/O7 I/O0 Figure 13.10 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification.

  • Page 443

    CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) Rev.

  • Page 444

    When software wait insertion is specified by WCR2, the external wait input RDY signal is also sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle.

  • Page 445

    100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to the SH7750. 16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set...

  • Page 446

    In addition to normal read and write access modes, fast page mode is supported for burst access. For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be increased, is supported. 1M × 16-bit SH7750 Series DRAM A12–A3 A9–A0 I/O15–I/O0...

  • Page 447

    256k × 16-bit SH7750 Series DRAM I/O15 I/O0 I/O15 I/O0 Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev. 6.0, 07/02, page 397 of 986...

  • Page 448

    256k × 16-bit SH7750 Series DRAM Area 3 I/O15 I/O0 Area 2 I/O15 I/O0 Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev. 6.0, 07/02, page 398 of 986...

  • Page 449

    DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7750 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM.

  • Page 450

    Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle. CKIO A25–A0 Column...

  • Page 451

    Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.18.

  • Page 452

    Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access.

  • Page 453

    CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. In the SH7750, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO mode is set, BE must be set to 1 in MCR.

  • Page 454

    Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.21 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7750 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an access.

  • Page 455

    CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev.

  • Page 456

    Tnop CKIO A25–A0 End of RAS down mode D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev.

  • Page 457

    CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev.

  • Page 458

    CKIO A25–A0 End of RAS down mode D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev.

  • Page 459

    RTCOR value, and if the two values are the same, a refresh request is generated and the BACK pin goes high. If the SH7750 Series’ external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted.

  • Page 460

    Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) • Self-Refresh The self-refreshing supported by the SH7750 Series is shown in figure 13.25. After the self-refresh is cleared, the refresh controller immediately generates a refresh request.

  • Page 461

    1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g.

  • Page 462

    SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series. TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 D63–D0 Figure 13.25 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at...

  • Page 463

    DRAM space. With the SH7750 Series, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.

  • Page 464

    512k × 16-bit × 2-bank SH7750 Series synchronous DRAM A12–A3 A9–A0 CKIO D63–D48 I/O15–I/O0 DQM7 DQMU DQM6 DQML A9–A0 D47–D32 I/O15–I/O0 DQMU DQM5 DQML DQM4 A9–A0 D31–D16 I/O15–I/O0 DQM3 DQMU DQM2 DQML A9–A0 D15–D0 I/O15–I/O0 DQM1 DQMU DQM0 DQML Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)

  • Page 465

    When A0, the LSB of the synchronous DRAM address, is connected to the SH7750 Series, with a 32-bit bus width it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7750, then connect pin A1 to pin A3.

  • Page 466

    DRAM; no new access command can be issued to the same bank during this cycle. In the SH7750 Series, the number of Tpc cycles is determined by the specification of bits TPC2– TPC0 in MCR, and commands are not issued for synchronous DRAM during this interval.

  • Page 467

    Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.28 Basic Timing for Synchronous DRAM Burst Read In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the data transfer cycle corresponding to the READ or READA command.

  • Page 468

    To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7750 Series waits for the end of the synchronous DRAM operation. The BS signal is asserted only in Td1.

  • Page 469

    Burst Write: The timing chart for a burst write is shown in figure 13.30. In the SH7750 Series, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output.

  • Page 470

    The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. As the SH7750 Series supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation.

  • Page 471

    Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.31 Basic Timing for Synchronous DRAM Single Write Rev. 6.0, 07/02, page 421 of 986...

  • Page 472

    RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.

  • Page 473

    that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh cycle or before bus release due to bus arbitration. Tc3 Tc4/Td1 Td2 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

  • Page 474

    Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.33 Burst Read Timing (RAS Down, Same Row Address) Rev.

  • Page 475

    Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 6.0, 07/02, page 425 of 986...

  • Page 476

    Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.35 Burst Write Timing Rev. 6.0, 07/02, page 426 of 986...

  • Page 477

    Tncp Tnop Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) Single-address DMA DACKn (SA: IO → memory) Normal write Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line.

  • Page 478

    Trw1 Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.37 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.

  • Page 479

    row address and the bank is different, the PRE command or ACTV command can be issued during the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle.

  • Page 480

    Tc1_A Tc1_B CKIO Bank Precharge-sel Address DQMn D63–D0 (read) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev.

  • Page 481

    Table 13.17 Cycles for which Pipeline Access is Possible Succeeding Access DMAC Dual DMAC Single Preceding Access Read Write Read Write Read Write Read Write DMAC dual Read Write DMAC single Read Write O: Pipeline access possible X: Pipeline access not possible Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing.

  • Page 482

    RTCNT cleared to 0 when RTCNT value RTCNT = RTCOR RTCOR-1 Time H'00000000 ≠ 000 RTCSR.CKS2–0 = 000 Refresh request Refresh request cleared by start of refresh cycle External bus Auto-refresh cycle Figure 13.39 Auto-Refresh Operation TRr1 TRr2 TRr3 TRr4 TRrw TRr5 CKIO...

  • Page 483

    RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7750 Series’ standby function, and is maintained even after recovery from standby mode other than through a power-on reset.

  • Page 484

    When a refresh request is generated, the BACK pin is negated (driven high). Therefore, normal refreshing can be performed by having the BACK pin monitored by a bus master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series.

  • Page 485

    To set burst read/write, CAS latency 1 to 3, wrap type = sequential, and burst length 4* or 8, supported by the SH7750, arbitrary data is written by byte-size access to the following addresses.

  • Page 486

    auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X. Synchronous DRAM mode register setting should be executed once only after power-on (reset) and before synchronous DRAM access, and no subsequent changes should be made.

  • Page 487

    TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Rev. 6.0, 07/02, page 437 of 986...

  • Page 488

    Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by the setting of the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register.

  • Page 489

    In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command;...

  • Page 490

    Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D31–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width to the SH7750R.

  • Page 491

    • Control signals required in this connection are RAS, CAS, RD/WR, CS3, DQM0−DQM7, and CKE. CS2 is not used. • Do not use partial-sharing mode. If you use this, correct operation is not guaranteed. SH7750R CKIO CASS RD/WR BANK1 BANK1 BANK1 BANK1 BANK0...

  • Page 492

    In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period.

  • Page 493

    CKIO A25–A5 A4–A0 D63–D0 (read) DACKn (SA: IO ← memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.47 Burst ROM Wait Access Timing Rev.

  • Page 494

    13.3.7 PCMCIA Interface In the SH7750 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1).

  • Page 495

    SA2 to SA0 and bit TC in the page table entry assistance register (PTEA). When the MMU is on (MMUCR.AT=1), the situation is the same as for the SH7750. In the SH7750 Series, access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values.

  • Page 496

    Table 13.18 Relationship between Address and CE when Using PCMCIA Interface Access Width Read/ Size Odd/ (Bits) * (Bits) Write Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Read Even Don’t — Invalid Read data care Don’t — Invalid Read data care Even Don’t...

  • Page 497

    Table 13.18 Relationship between Address and CE when Using PCMCIA Interface (cont) Access Width Read/ Size Odd/ (Bits) * (Bits) Write Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing * Even —...

  • Page 498

    A25–A0 A25–A0 D15–D0 D7–D0 D15–D0 PC card D15–D8 (memory I/O) SH7750 Series Card detection CD1, CD2 circuit Output A25–A0 Port D7–D0 D15–D0 D15–D8 PC card (memory I/O) Card CD1, CD2 detection circuit Figure 13.49 Example of PCMCIA Interface Rev. 6.0, 07/02, page 448 of 986...

  • Page 499

    Memory Card Interface Basic Timing: Figure 13.50 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.51 shows the PCMCIA memory card interface wait timing. Tpcm1 Tpcm2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

  • Page 500

    Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Notes: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. * SH7750S, SH7750R only Figure 13.51 Wait Timing for PCMCIA Memory Card Interface Rev.

  • Page 501

    Common memory (64 MB) Virtual Access address space by CS5 wait Physical I/O controller addresses 1 kB IO 1 Virtual Access page address space by CS6 wait IO 1 controller Common IO 2 memory 1 Common Card 1 memory 2 on CS5 IO 2 Attribute memory...

  • Page 502

    Tpci1 Tpci2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.53 Basic Timing for PCMCIA I/O Card Interface Rev. 6.0, 07/02, page 452 of 986...

  • Page 503

    Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 Wait Timing for PCMCIA I/O Card Interface Rev.

  • Page 504

    Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.

  • Page 505

    13.3.8 MPX Interface If the MD6 pin is set to 0 in a power-on reset by the RESET pin, the MPX interface for normal memory is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and the MEMMODE, A4MPX, and AIMPX bits in BCR3.

  • Page 506

    SH7750 Series MPX device CKIO D63–D0 I/O63–I/O0 Figure 13.56 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2.

  • Page 507

    Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.57 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) Rev.

  • Page 508

    Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.58 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev.

  • Page 509

    Tmd1 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.59 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev. 6.0, 07/02, page 459 of 986...

  • Page 510

    Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev.

  • Page 511

    Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.

  • Page 512

    Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.62 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.

  • Page 513

    Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.

  • Page 514

    Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.64 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.

  • Page 515

    Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.65 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev.

  • Page 516

    Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.66 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev.

  • Page 517

    Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.67 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev.

  • Page 518

    Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.68 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev.

  • Page 519

    Figure 13.69 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 469 of 986...

  • Page 520

    Figure 13.70 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 470 of 986...

  • Page 521

    Figure 13.71 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 471 of 986...

  • Page 522

    Figure 13.72 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 6.0, 07/02, page 472 of 986...

  • Page 523

    32-byte boundary. The bus is not released during this period. Figure 13.73 shows an example of byte control SRAM connection to the SH7750, and figures 13.74 to 13.76 show examples of byte control SRAM read cycle.

  • Page 524

    64k × 16-bit SH7750 Series SRAM A18–A3 A15–A0 I/O15–I/O0 D63–D48 A15–A0 D47–D32 I/O15–I/O0 A15–A0 D31–D16 I/O15–I/O0 A15–A0 D15–D0 I/O15–I/O0 Figure 13.73 Example of 64-Bit Data Width Byte Control SRAM Rev. 6.0, 07/02, page 474 of 986...

  • Page 525

    CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.74 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 6.0, 07/02, page 475 of 986...

  • Page 526

    CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.75 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 6.0, 07/02, page 476 of 986...

  • Page 527

    CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev.

  • Page 528

    13.2.5, Wait Control Register (WCR1). When the SH7750 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7750 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed.

  • Page 529

    Twait Twait A25–A0 D31–D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.77 Waits between Access Cycles Rev. 6.0, 07/02, page 479 of 986...

  • Page 530

    13.3.11 Bus Arbitration The SH7750 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.

  • Page 531

    As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7750 Series.

  • Page 532

    CKIO Asserted for at least 2 cycles Negated within 2 cycles A25–A0 D63–D0 (write) Master mode device access Must be asserted for Must be negated within 2 cycles at least 2 cycles A25–A0 D63–D0 (write) Slave mode device access Master access Slave access Master access Figure 13.78 Arbitration Sequence...

  • Page 533

    BACK signal is negated even while the BREQ signal is asserted to request the slave to relinquish the bus. When the SH7750 Series is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitration in the case of a slave designed independently...

  • Page 534

    by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the BACK signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence.

  • Page 535

    13.3.14 Partial-Sharing Master Mode In partial-sharing master mode, area 2 only is shared with other devices, and other areas can be accessed at all times. Partial-sharing master mode can be set by setting master mode with the external mode pins, and setting the PSHR bit to 1 in BCR1 in the initialization procedure in a power-on reset.

  • Page 536

    2, while the master performs initialization of the memory connected to it. If the SH7750 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the BREQ enable bit (BCR1.BREQEN) is set to 1.

  • Page 537

    1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. Synchronous DRAM Mode Register Setting (SH7750, SH7750S Only): The following conditions must be satisfied when setting the synchronous DRAM mode register.

  • Page 538

    Rev. 6.0, 07/02, page 488 of 986...

  • Page 539

    14.1 Overview The SH7750 and SH7750S include an on-chip four-channel direct memory access controller (DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC).

  • Page 540

    (single only), etc., specified by the external device. Although channel 0 has no request queue, there are four request queues for each of the other channels: i.e., channels 1 to 3 in the SH7750 or SH7750S, and channels 1 to 7 in the SH7750R.

  • Page 541

    • Channel 6 (SH7750R only): Dual address mode only. • Channel 7 (SH7750R only): Dual address mode only.  DDT mode channel function • Channel 0: Single address mode. External requests are accepted Dual address mode (SH7750S, SH7750R) • Channel 1: Single or dual address mode. External requests are accepted. •...

  • Page 542

    14.1.2 Block Diagram (SH7750, SH7750S) Figure 14.1 shows a block diagram of the DMAC. DMAC module Count SARn control Register DARn control DMATCRn Activation On-chip control peripheral CHCRn module DMAOR Request priority SCI, SCIF control DACK0, DACK1 DRAK0, DRAK1 interface...

  • Page 543

    14.1.3 Pin Configuration (SH7750, SH7750S) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name Abbreviation Function DREQ0 DMA transfer Input DMA transfer request input from request external device to channel 0 DREQ acceptance DRAK0...

  • Page 544

    (ID [1] = DRAK1, ID [0] = DACK1) 14.1.4 Register Configuration (SH7750, SH7750S) Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers are allocated to each channel, and an additional control register is shared by all four channels.

  • Page 545

    *1 Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. *2 In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from external I/O devices using the DTR format are possible In DDT mode.

  • Page 546

    [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2. In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from external I/O devices using the DTR format are possible In DDT mode.

  • Page 547

    14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...

  • Page 548

    14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: Initial value: R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — —...

  • Page 549

    14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: SSA2 SSA1 SSA0 DSA2 DSA1 DSA0 Initial value: R/W: Bit: — — — — Initial value: R/W: (R/W) (R/W) Bit: Initial value: R/W: Bit: — Initial value: R/W: R/(W) Note: The TE bit can only be written with 0 after being read as 1, to clear the flag. The RL, AM, AL, and DS bits may be absent, depending on the channel.

  • Page 550

    Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 31: SSA2 Bit 30: SSA1 Bit 29: SSA0 Description Reserved in PCMCIA access (Initial value) Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space...

  • Page 551

    Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description Reserved in PCMCIA access (Initial value) Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space...

  • Page 552

    In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is valid for CHCR1 to CHCR3 in the SH7750. In the SH7750S, this bit is valid for CHCR0 to CHCR3. (DDT mode: TDACK)

  • Page 553

    Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 16: AL Description Active-high output (Initial value) Active-low output Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address.

  • Page 554

    *3 In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56] (MD1, MD0 bits) specification for channel 0 only. *4 In DDT mode: [SH7750] An external request specification should be set for channels 1 to 3. For channel 0, only single address mode can be set with the DTR format.

  • Page 555

    Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM Description Cycle steal mode (Initial value) Burst mode Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For external memory access, the setting of these bits serves as the access size in section 14.3, Operation.

  • Page 556

    Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1.

  • Page 557

    14.2.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — Initial value: R/W: Bit: — —...

  • Page 558

    Note: When external request mode is used in the SH7750S, recommend setting COD to 1 permanently. Bit 4 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.

  • Page 559

    Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1.

  • Page 560

    14.3 Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.

  • Page 561

    Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Illegal address check (reflected in AE bit) NMIF, AE, TE = 0? Transfer request issued? Bus mode, transfer request mode, detection method Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR NMIF or DMATCR = 0?

  • Page 562

    14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.

  • Page 563

    Table 14.4 Selecting External Request Mode with RS Bits Address Mode Transfer Source Transfer Destination Dual address External memory External memory mode or memory-mapped or memory-mapped external device, or external device, or external device with external device with DACK DACK Single address External memory External device...

  • Page 564

    When DMA transfer is restarted, check whether a DMA transfer request is being held. On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF).

  • Page 565

    2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. A DMA transfer request by means of an input capture interrupt can be canceled by setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU.

  • Page 566

    Transfer on channel 0 Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 Initial priority order priority. CH1 > CH2 > CH3 > CH0 Priority order after transfer Transfer on channel 1 When channel 1 is given the Initial priority order CH0 >...

  • Page 567

    1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby).

  • Page 568

    14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output.

  • Page 569

    DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External External address data bus SH7750 Series External memory DMAC External device with DACK DACK : Data flow Figure 14.5 Data Flow in Single Address Mode...

  • Page 570

    CKIO Address output to external memory A28–A0 space Data output from external device D63–D0 with DACK DACK DACK signal to external device with DACK signal to external memory space (a) From external device with DACK to external memory space CKIO Address output to external memory A28–A0 space...

  • Page 571

    CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the BSC’s data buffer in the read cycle, then written to the other external memory in the write cycle.

  • Page 572

    CKIO Transfer source Transfer destination A26–A0 address address D63–D0 DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–...

  • Page 573

    Bus returned to CPU Bus cycle DMAC DMAC DMAC DMAC Read Write Read Write Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied.

  • Page 574

    Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Request Transfer Size Usable Mode Type of Transfer Mode Mode (Bits) Channels 8/16/32/64/32B 0, 1 (2, 3) * Single External device with DACK External and external memory 8/16/32/64/32B 0, 1 (2, 3) * External device with DACK External...

  • Page 575

    (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7750 Series in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal Mode...

  • Page 576

    2. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. *1 In SH7750, the bus width must be 64 bits *2 DACK output setting in dual address mode transfer...

  • Page 577

    DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 DMAC channel 1 DMAC channel 0 and DMAC channel 1 burst mode channel 1 round robin burst mode mode Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing)

  • Page 578

    In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If DREQ is not detected at this time, sampling is executed in every subsequent cycle.

  • Page 579

    For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only.

  • Page 580

    Figure 14.12 Dual Address Mode/Cycle Steal Mode DREQ DREQ (Level Detection), DACK (Read Cycle) DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 530 of 986...

  • Page 581

    Figure 14.13 Dual Address Mode/Cycle Steal Mode DREQ DREQ DREQ (Edge Detection), DACK (Read Cycle) External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 531 of 986...

  • Page 582

    Figure 14.14 Dual Address Mode/Burst Mode DREQ (Level Detection), DACK (Read Cycle) DREQ DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 532 of 986...

  • Page 583

    Figure 14.15 Dual Address Mode/Burst Mode DREQ DREQ DREQ (Edge Detection), DACK (Read Cycle) External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 533 of 986...

  • Page 584

    Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → → → → External Bus Rev. 6.0, 07/02, page 534 of 986...

  • Page 585

    Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → → → → On-Chip SCI (Level Detection) Rev. 6.0, 07/02, page 535 of 986...

  • Page 586

    Figure 14.18 Single Address Mode/Cycle Steal Mode DREQ DREQ (Level Detection) DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 536 of 986...

  • Page 587

    Figure 14.19 Single Address Mode/Cycle Steal Mode DREQ (Edge Detection) DREQ DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 537 of 986...

  • Page 588

    Figure 14.20 Single Address Mode/Burst Mode DREQ DREQ (Level Detection) DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 538 of 986...

  • Page 589

    Figure 14.21 Single Address Mode/Burst Mode DREQ DREQ (Edge Detection) DREQ External Bus → → → → External Bus/DREQ Rev. 6.0, 07/02, page 539 of 986...

  • Page 590

    Figure 14.22 Single Address Mode/Burst Mode DREQ (Level Detection)/32-Byte Block Transfer DREQ DREQ External Bus → → → → External Bus/DREQ (Bus Width: 64 Bits, SDRAM: Row Hit Write) Rev. 6.0, 07/02, page 540 of 986...

  • Page 591

    14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer.

  • Page 592

    Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0. • The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1.

  • Page 593

    2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU.

  • Page 594

    14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions...

  • Page 595

    14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC.

  • Page 596

    After the initial settings have been made in the DMAC channel 0 control register by means of normal data transfer mode (channel 0) in the SH7750, or after the initial settings have been made in the DMAC channel 0 control register from the CPU or by means of normal data transfer mode (channel 0) in the SH7750S, the DDT module asserts a data transfer request for the DMAC by setting DTR format ID = 00, MD = 00, and SZ ≠...

  • Page 597

    14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. /DREQ0 /DRACK0 /DREQ1 /DACK0 SH7750 Series ID1, ID0/DRAK1, DACK1 External device D63–D0 A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode •...

  • Page 598

    47–32 is invalid. In the SH7750, only single address mode can be set in normal data transfer mode (channel 0). With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01,...

  • Page 599

    • 011: Quadword size (64-bit) specification • 100: 32-byte block transfer specification • 101: Setting prohibited • 110: Request queue clear specification • 111: Transfer end specification Bit 60: Read/Write (R/W) • 0: Memory read specification • 1: Memory write specification Bits 59 and 58: Channel Number (ID1, ID0) •...