Hitachi SH7750 Hardware Manual page 480

Tc1_A Tc1_B
CKIO
Bank
Precharge-sel H/L H/L
c_A c_B
Address
RD/
DQMn
D63–D0
a1 a2 a3 a4 b1 b2
(read)
CKE
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle
Rev. 6.0, 07/02, page 430 of 986