Table 21.3 Configuration Of The Boundary Scan Register (2) - Hitachi SH7750 Hardware Manual

Table 21.3 Configuration of the Boundary Scan Register (2)

No. Pin Name
235 D56
234 D56
233 D56
232 D55
231 D55
230 D55
229 D31
228 D31
227 D31
226 D16
225 D16
224 D16
223 D30
222 D30
221 D30
220 D17
219 D17
218 D17
217 D29
216 D29
215 D29
214 D18
213 D18
212 D18
211 D28
210 D28
209 D28
208 D19
207 D19
206 D19
205 D27
204 D27
203 D27
202 D20
201 D20
200 D20
199 D26
198 D26
197 D26
Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Rev. 6.0, 07/02, page 808 of 986
Type No. Pin Name
IN 196 D21
CTL 195 D21
OUT 194 D21
IN 193 D25
CTL 192 D25
OUT 191 D25
DREQ1
IN 190
DREQ0
CTL 189
OUT 188 RXD
IN 187 D22
CTL 186 D22
OUT 185 D22
IN 184 D24
CTL 183 D24
OUT 182 D24
IN 181 D23
CTL 180 D23
OUT 179 D23
WE7/CAS7/DQM7/REG
IN 178
WE7/CAS7/DQM7/REG
CTL 177
WE6/CAS6/DQM6
OUT 176
WE6/CAS6/DQM6
IN 175
WE3/CAS3/DQM3/ICIOWR CTL
CTL 174
WE3/CAS3/DQM3/ICIOWR OUT
OUT 173
WE2/CAS2/DQM2/ICIORD CTL
IN 172
WE2/CAS2/DQM2/ICIORD OUT
CTL 171
OUT 170 RD/WR
IN 169 RD/WR
RD/CASS/FRAME
CTL 168
RD/CASS/FRAME
OUT 167
RAS
IN 166
RAS
CTL 165
CS2
OUT 164
CS2
IN 163
CS3
CTL 162
CS3
OUT 161
IN 160 DRAK0
CTL 159 DRAK0
OUT 158 DRAK1
Type No. Pin Name
IN 157 DRAK1
CTL 156 A2
OUT 155 A2
IN 154 A3
CTL 153 A3
OUT 152 A4
IN 151 A4
IN 150 A5
IN 149 A5
IN 148 A6
CTL 147 A6
OUT 146 A7
IN 145 A7
CTL 144 A8
OUT 143 A8
IN 142 A9
CTL 141 A9
OUT 140 A10
CTL 139 A10
OUT 138 A11
CTL 137 A11
OUT 136 A12
135 A12
134 A13
133 A13
132 A14
CTL 131 A14
OUT 130 A15
CTL 129 A15
OUT 128 A16
CTL 127 A16
OUT 126 A17
CTL 125 A17
WE0/CAS0/DQM0
OUT 124
WE0/CAS0/DQM0
CTL 123
WE1/CAS1/DQM1
OUT 122
WE1/CAS1/DQM1
CTL 121
WE4/CAS4/DQM4
OUT 120
WE4/CAS4/DQM4
CTL 119
Type
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT