Hitachi SH7750 Hardware Manual page 14

Section
14.6 Configuration of the
DMAC (SH7750R)
14.7 Register Descriptions
(SH7750R)
14.8 Operation (SH7750R)
14.9 Usage Notes
15.2.8 Serial Port Register
(SCSPTR1)
16.1.2 Block Diagram
16.1.3 Pin Configuration
16.2.6 Serial Control
Register (SCSCR2)
16.2.7 Serial Status Register
(SCFSR2)
16.2.9 FIFO Control Register
(SCFCR2)
16.2.11 Serial Port Register
(SCSPTR2)
16.3.2 Serial Operation
17.1 Overview
17.3.2 Pin Connections
18.1.3 Pin Configuration
19.1.2 Block Diagram
19.1.4 Register Configuration 753
19.2.3 On-Chip Peripheral
Module Interrupts
Rev. 6.0, 07/02, page xiv of I
Page Item
574
579
586
591 4.
592 9.
609 Bit 7
659 Figure 16.1 Block Diagram
of SCIF
660 Table 16.1 SCIF Pins
667 Bit 1
669 Bit 7—Receive Error (ER)
672 Bit 3—Framing Error (FER)
672 Bit 2—Parity Error (PER)
676 Bits 10 to 8
Figure 16.6 MRESET/SCK2
Pin
689 Figure 16.6 Sample SCIF
Initialization Flowchart
696 Serial Data Reception
703
711
740 Table 18.3 SCIF I/O Port
Pins
752 Figure 19.1 Block Diagram
of INTC
Table 19.2 INTC Registers
757, 758
Description
Newly added
Newly added
Added
Description amended
Newly added
Description amended
Amended
Note changed
Description amended
Note description
changed
Description changed
Description changed
SH7750R added
Deleted
Amended
Description added to 5.
Description amended
Description deleted
Amended
Amended
Description added to
table, Notes added and
amended
Description added and
amended