Hitachi SH7750 Hardware Manual page 5

List of Items Revised or Added for This Version
Section
1.1 SH7750 Series (SH7750,
SH7750S, SH7750R)
Features
1.2 Block Diagram
1.3 Pin Arrangement
1.4 Pin Functions
2.7 Processor Modes
3.2 Register Descriptions
3.3.1 Physical Address
Space
Page Item
1
4 to 8 Table 1.1 SH7750 Series
Features
9 Figure 1.1 Block Diagram of
SH7750 Series Functions
10 to 12 Figure 1.2 to 1.4
13 to 40 Table 1.2 to 1.4
55
61 Figure 3.2 MMU-Related
Registers
62 3. Page table entry
assistance register (PTEA)
62 1. Page table entry high
register (PTEH),
6. MMU control register
(MMUCR)
64 to 67
Description
Description amended
and added
Description added for
LSI, and description
and Note added for
Clock pulse generator
(CPG)
SH7750 and SH7750S
added to cache memory
Cache memory
[SH7750R] added to
table
Description added for
Direct memory access
controller (DMAC) and
Timer unit (TMU)
SH7750R table added
to Product lineup
Notes 1, 2, 3 added
I cache 8 KB and 0
cache 16 KB deleted
from table
SH7750R added, and
description amended
Table and note
amended
Description deleted
Amended
SH7750R added after
SH7750S
Description added
Description added
Rev. 6.0, 07/02, page v of I