Pcmcia Control Register (Pcr) - Hitachi SH7750 Hardware Manual

Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-
before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using
the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is
issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When
the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous
DRAM, after waiting for the end of any currently executing external bus cycle. All refresh
requests for memory in the self-refresh state are ignored.
Bit 1: RMODE
0
1
Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when
using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of
memory other than DRAM. Set this bit to 1 only when DRAM is used.
13.2.9

PCMCIA Control Register (PCR)

The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the OE
and WE signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6.
The OE and WE signal assertion width is set by the wait control bits in the WCR2 register. For
details of access to PCMCIA, see section 13.3.7, PCMCIA Interface.
PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2
Initial value:
R/W:
Bit:
Bit name: A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0
Initial value:
R/W:
Description
CAS-before-RAS refreshing is performed (when RFSH = 1)
Self-refreshing is performed (when RFSH = 1)
15 14
0 0
R/W R/W
7 6
0 0
R/W R/W
13 12 11
0 0
R/W R/W R/W
5 4
0 0
R/W R/W R/W
10 9
0 0 0
R/W R/W
3 2 1
0 0 0
R/W R/W
Rev. 6.0, 07/02, page 359 of 986
(Initial value)
8
0
R/W
0
0
R/W