Figure 420. Swj Debug Port; Mechanism To Select The Jtag-Dp Or The Sw-Dp - ST STM32F205 series Reference Manual

RM0033
Figure 420
TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
32.3.1

Mechanism to select the JTAG-DP or the SW-DP

By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG
sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
32.4 Pinout and debug port pins
The STM32F20x and STM32F21x MCUs are available in various packages with different
numbers of available pins. As a result, some functionality (ETM) related to pin availability
may differ between packages.

Figure 420. SWJ debug port

shows that the asynchronous TRACE output (TRACESWO) is multiplexed with
RM0033 Rev 8
Debug support (DBG)
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