Scan Mode; Injected Channel Management; Table 75. Analog Watchdog Channel Selection - ST STM32F423 Reference Manual

RM0430
Channels guarded by the analog
None
All injected channels
All regular channels
All regular and injected channels
(1)
Single
(1)
Single
(1)
Single
1. Selected by the AWDCH[4:0] bits
13.3.8

Scan mode

This mode is used to scan a group of analog channels.
The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for
regular channels) or in the ADC_JSQR register (for injected channels). A single conversion
is performed for each channel of the group. After each end of conversion, the next channel
in the group is converted automatically. If the CONT bit is set, regular channel conversion
does not stop at the last selected channel in the group but continues again from the first
selected channel.
If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data
converted from the regular group of channels (stored in the ADC_DR register) to SRAM
after each regular channel conversion.
The EOC bit is set in the ADC_SR register:
•
At the end of each regular group sequence if the EOCS bit is cleared to 0
•
At the end of each regular channel conversion if the EOCS bit is set to 1
The data converted from an injected channel are always stored into the ADC_JDRx
registers.
13.3.9

Injected channel management

Triggered injection
To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.
1. Start the conversion of a group of regular channels either by external trigger or by
setting the SWSTART bit in the ADC_CR2 register.
2. If an external injected trigger occurs or if the JSWSTART bit is set during the
conversion of a regular group of channels, the current conversion is reset and the
injected channel sequence switches to Scan-once mode.
3. Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
If a regular event occurs during an injected conversion, the injected conversion is not

Table 75. Analog watchdog channel selection

watchdog
injected channel
regular channel
regular or injected channel
ADC_CR1 register control bits (x = don't care)
AWDSGL bit
x
0
0
0
1
1
1
RM0430 Rev 8
Analog-to-digital converter (ADC)
AWDEN bit JAWDEN bit
0
0
1
1
0
1
1
0
1
0
1
1
0
1
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