Tim9/12 Event Generation Register (Timx_Egr) - ST STM32F207 Series Reference Manual

RM0033
Bit 0 UIF: Update interrupt flag
– At overflow and if UDIS='0' in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS='0' and
– When CNT is reinitialized by a trigger event (refer to the synchro control register
15.4.6

TIM9/12 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/compare 2 generation
Bit 1 CC1G: Capture/compare 1 generation
Bit 0 UG: Update generation
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
UDIS='0' in the TIMx_CR1 register.
description), if URS='0' and UDIS='0' in the TIMx_CR1 register.
12 11 10 9
Reserved
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
refer to CC1G description
This bit is set by software to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
the CC1IF flag is set, the corresponding interrupt is sent if enabled.
If channel CC1 is configured as input:
The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. The prescaler counter
is also cleared and the prescaler ratio is not affected. The counter is cleared.
General-purpose timers (TIM9 to TIM14)
8 7 6
TG
w
RM0033 Rev 9
5 4 3 2
CC2G
Reserved
w
1 0
CC1G UG
w w
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