Block Diagram Of Clock Generation Controller - Fujitsu FR60 Hardware Manual

3.12.5 Block Diagram of Clock Generation Controller

This section provides a block diagram of the clock generation controller.
■ Block Diagram
Figure 3.12-1 shows a block diagram of the clock generation controller. Refer to "3.12.6
Register of Clock Generation Controller" for the detail of registers in Figure 3.12-1.
Figure 3.12-1 Block Diagram of Clock Generation Controller
X0 Oscilla-
tion
circuit
X1
Internal interrupt
Internal reset
INIT pin
[Clock generator]
DIVR0,1 registers
CPU clock division
Peripheral clock division
External bus clock division
CLKR register
PLL
1/2
[Stop and sleep controller]
STCR register
Status
transition
control
circuit
[Reset source circuit]
RSRR register
[Watchdog controller]
Time base counter
CTBR register
TBCR register
Overflow detection F/F
Interrupt enable
CHAPTER 3 CPU AND CONTROL UNITS
Selector CPU clock
Peripheral clock
Selector
External bus clock
Selector
Stop status
Sleep status
Reset
occurrence
Internal reset (RST)
F/F
Reset
Internal reset (INIT)
occurrence
F/F
Watchdog F/F
Counter clock
Selector
Time-base timer
interrupt request
109