Fujitsu FR60 Hardware Manual page 88

CHAPTER 3 CPU AND CONTROL UNITS
[bit0] C (Carry flag)
This bit indicates whether a carry or a borrow has occurred from the highest bit in the
operation.
Table 3.4-6 shows the settings of this bit.
Table 3.4-6 Functions of Carry Flag (C)
Value
0
1
The initial state of this bit upon reset is undefined.
❍ System condition code register (SCR)
Figure 3.4-10 shows the configuration of the system condition code register (SCR: System
Condition code Register).
Figure 3.4-10 Register Configuration of System Condition Code Register
The following describes the functions of the system condition code register (SCR) bits.
[bit10, bit9] D1, D0 (Step division flag)
These bits hold the intermediate data obtained when step division is executed.
Do not change these bits while division processing is being executed.
To perform other processing while executing a step division, save and restore the value of
the PS register to ensure that the step division is restarted.
The initial state of this bit upon reset is undefined.
To set these bits, execute the DIV0S instruction with the dividend and the divisor to be
referenced.
To forcibly clear these bits, execute the DIV0U instruction.
• Simultaneous acceptance of DIV0S/DIV0U instruction, user interrupt and NMI
Do not perform the process expecting the D0 and D1 bits in the PS register before EIT
branching in the EIT processing routine.
• The D0 and D1 bits in the PS register may not indicate the correct value if the operation is
stopped by break or step execution immediately before the DIV0S/DIV0U instruction.
Note, however, that the correct value will be calculated after return.
68
Indicates that no carry and borrow have occurred.
Indicates that a carry or borrow has occurred.
bit 10 9
D1 D0
Description
8 [Initial value]
XX0
T
B