Fujitsu FR60 Hardware Manual page 633

TMCSR
Bit Configuration of the Control Status Register
(TMCSR) ........................................... 272
Bit Functions of the Control Status Register
(TMCSR) ........................................... 272
TMR
Bit Configuration of the 16-bit Timer Register
(TMR:TMR2 to TMR0)....................... 275
TMRLR
Bit Configuration of the 16-bit Reload Register
(TMRLR:TMRLR2 to TMRLR0)......... 276
Trace
Operation of Step Trace Trap .............................. 92
Transfer
Block Transfer ................................................. 432
Burst Transfer.................................................. 433
Demand Transfer ............................................. 434
Example of Slave Address and Data Transfer ..... 473
Flow of Data during 2-Cycle Transfer ................ 435
Flow of Data during Fly-By Transfer ................. 437
If an External Pin Transfer Request is Re-entered
During Transfer .................................. 431
If Another Transfer Request Occurs during Block
Transfer ............................................. 431
Timing of the DREQ Pin Input for Continuing
Transfer Over the Same Channel .......... 430
Timing of Transfer other than Demand
Transfer ............................................. 439
Transfer between External I/O and External
Memory ............................................. 431
Transfer Address
Transfer Address.............................................. 406
Transfer Count
Transfer Count and Transfer End....................... 407
Transfer Count Control
Transfer Count Control..................................... 418
Transfer Data
Transfer Data Format ............................... 374, 375
Transfer End
Transfer Count and Transfer End....................... 407
Transfer Instructions
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions......................................... 583
Register-to-Register Transfer Instructions .......... 585
Transfer Mode
Transfer Mode ................................................. 405
Transfer Mode Settings..................................... 441
Transfer Request
Transfer Request Acceptance and Transfer ......... 421
Transfer Sequence
Selection of the Transfer Sequence .................... 410
Transfer Source/Transfer Destination Address
Setting Register
Bit Configuration of Transfer Source/Transfer
Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to
DMADA4)..........................................400
Detailed Bit of Transfer Source/Transfer Destination
Address Setting Registers (DMASA0 to
DMASA4/DMADA0 to DMADA4)......400
Transfer Type
Transfer Type...................................................406
Transition
State of Device and Each Transition ...................132
Transition Requests
Priority of State Transition Requests...................135
Trap
Coprocessor Error Trap .......................................93
EIT (Exception,Interrupt,and Trap) ......................79
No-coprocessor Trap...........................................93
Operation of Step Trace Trap...............................92
U
UART
Example of Using the UART .............................380
Selecting a Clock for the UART.........................373
UART .................................................................4
UART Operating Modes ...................................373
UART Registers ...............................................362
Undefined Instruction
Operation of Undefined Instruction Exception .......92
Underflow Operation
Underflow Operation ........................................278
Unused Input Pins
Unused Input Pins...............................................32
User Interrupt
Operation of User Interrupt/NMI..........................90
User Stack Pointer
User Stack Pointer (USP) ....................................65
User Tasks
User Tasks .......................................................519
USP
User Stack Pointer (USP) ....................................65
UTIM
U-TIMER (UTIM:UTIM2 to UTIM0) ................309
UTIMC
Bit Details of U-TIMER Control Register
(UTIMC) ............................................310
Precautions on the U-TIMER Control Register
(UTIMC) ............................................312
U-TIMER Control Register (UTIMC:UTIMC2 to
UTIMC0)............................................310
U-TIMER
Example of Setting Baud Rates and U-TIMER Reload
Values ................................................382
INDEX
613