Data Bus - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series
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14.5 Data Bus

This section shows the flow of data during 2-cycle transfer and fly-by transfer.
■ Flow of Data during 2-Cycle Transfer
Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer.
Figure 14.5-1 Examples of 2-Cycle Transfer (Continued on Next Page)
MB91301
Read cycle
I-bus
Bus controller
D-bus
MB91301
Read cycle
I-bus
Bus controller
D-bus
MB91301
Read cycle
I-bus
Bus controller
D-bus
External area => external area transfer
DMAC
X-bus
Data buffer
F-bus
RAM
I/O
External area => internal RAM area transfer
DMAC
X-bus
Data buffer
F-bus
RAM
I/O
External area => built-in I/O area transfer
DMAC
X-bus
Data buffer
F-bus
RAM
I/O
CHAPTER 14 DMA CONTROLLER (DMAC)
MB91301
DMAC
Write cycle
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
MB91301
DMAC
Write cycle
I-bus
Bus controller
D-bus
Data buffer
F-bus
RAM
MB91301
DMAC
Write cycle
I-bus
Bus controller
Data buffer
D-bus
F-bus
RAM
X-bus
I/O
X-bus
I/O
X-bus
I/O
(Continued)
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