Fujitsu FR60 Hardware Manual page 135

■ Time Base Counter Control Register (TBCR)
Figure 3.12-4 shows the configuration of the time base counter control register (TBCR) bits.
Figure 3.12-4 Configuration of Time Base Counter Control Register (TBCR) Bits
Address: 00000482
Initial value (INIT)
Initial value (RST)
The time base counter control register (TBCR) controls time-base timer interrupts, among other
things.
This register enables time-base timer interrupts, selects an interrupt interval time, and sets an
optional function for the reset operation.
The following describes the functions of the time base counter control register (TBCR) bits.
[bit15] TBIF (Time-base timer Interrupt Flag)
This bit is the time-base timer interrupt flag. It indicates that the interval time (TBC2 to TBC0
bits, which are bit13 to bit11) specified by the time base counter has elapsed.
A time-base timer interrupt request is generated if this bit is set to "1" when interrupts are
enabled by bit14 (TBIE bit, TBIE=1).
Table 3.12-11 Function of Time-base timer Interrupt Flag (TBIF)
TBIF
Clear source
Set source
• This bit is initialized to "0" by a reset (RST).
• This bit is readable and writable, although only "0" can be written to it. Writing "1" does not
change the bit value. The value read by a read-modify-write instruction is always "1".
[bit14] TBIE (Time-base Timer Interrupt Enable)
This bit is the time-base timer interrupt request output enable bit.
It controls output of an interrupt request when the interval time of the time base counter has
elapsed. A time-base timer interrupt request is generated if the TBIF bit is set to "1" when
this bit is set to "1".
Table 3.12-12 Function of time-base timer interrupt request output enable bit (TBIE)
TBIE
0
1
• This bit is initialized to "0" by a reset (RST).
• This bit is readable and writable.
bit 7 6 5
TBIF TBIE TBC2
H
R/W R/W R/W
0 0 X
0 0 X
An instruction writes "0".
The specified interval time elapses (the trailing edge of the time base
counter is detected).
Time-base timer interrupt request output disabled (initial value)
Time-base timer interrupt request output enabled
CHAPTER 3 CPU AND CONTROL UNITS
4 3 2
TBC1 TBC0 - SYNCR SYNCS
R/W R/W R/W R/W
X X X
X X X
Function
Function
1 0
R/W
0 0
X X
115