Fujitsu FR60 Hardware Manual page 308

CHAPTER 7 PPG TIMER
[bit8] (Reserved)
This bit is unused bit.
[bit7, bit6] EGS1, EGS0: Trigger input edge selection bit
This bit selects the valid edge for the activation source selected by the general control
register 1.
When the software trigger bit is set to "1", a software trigger is enabled regardless of the
mode selected.
Table 7.3-6 Setting of trigger input edge selection
[bit5] IREN: Interrupt request enable bit
This bit specifies whether to enable interrupt requests.
Table 7.3-7 Interrupt request setting
[bit4] IRQF: Interrupt request flag
When bit5 (IREN) is set to "Enabled", and the interrupt source specified by bit3 and bit2
(IRS1 and IRS0) occurs, this bit is set and an interrupt request is issued to the CPU. In
addition, when activation of DMA transfer is specified, DMA transfer is started.
This bit is cleared when a value of "0" is written or the clear signal is received from the
DMAC.
The value of this bit does not change even if there is an attempt to set it to "1" via a write
operation.
When this bit is read by read-modify-write instructions, "1" is returned regardless of the bit
value.
[bit3, bit2] IRS1, IRS0: Interrupt source selection bit
These bits select the interrupt source that sets bit4 (IRQF).
Table 7.3-8 Setting of Interrupt Source Selection
IRS1
0
0
1
1
288
EGS1
0
0
1
1
IREN
0 Disabled (initial value)
1 Enabled
IRS0
0 Software trigger or trigger input (initial value)
1 Counter borrow (cycle match)
0 Duty match
1 Counter borrow (cycle match) or duty match
EGS0
0 Disabled (initial value)
1 Rising edge
0 Falling edge
1 Both edges
Function
Interrupt source
Edge selection