Fujitsu FR60 Hardware Manual page 628

INDEX
Monitor Debugger
Emulator Debugger/Monitor Debugger .............. 571
Multiple Channels
Activating Multiple Channels with the GCN ....... 303
Multiply and Divide Registers
Multiply and Divide Registers (MDH/MDL) ........ 65
Multiply Instructions
Multiply Instructions ........................................ 582
N
NC
Treatment of NC and OPEN Pins......................... 33
Negate Timing
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is
Stopped .............................................. 428
NMI
Block Diagram of the External Interrupt and NMI
Controller ........................................... 316
External Interrupt and NMI Controller
Registers ............................................ 317
Level Mask for Interrupt and NMI ....................... 81
NMI........................................................ 322, 340
Operation of User Interrupt/NMI ......................... 90
No Delay
Normal Branch (No Delay) Instructions ............. 586
No-coprocessor Trap
No-coprocessor Trap .......................................... 93
Normal Branch
Normal Branch (No Delay) Instructions ............. 586
Normal Branch Macro Instructions
20-bit Normal Branch Macro Instructions ........... 591
32-bit Normal Branch Macro Instructions ........... 593
Normal Polarity
Interrupt Sources and Timing Chart (PPG Output:
Normal Polarity) ................................. 301
Normal Reset
Normal Reset Operation.................................... 101
Notes
Notes .............................................................. 487
O
Objects
Objects............................................................ 519
One-shot Operation
One-shot Operation .......................................... 299
OPEN Pins
Treatment of NC and OPEN Pins......................... 33
Operating Modes
Operating Modes.............................................. 140
Operating States
Operating States of the Counter ......................... 279
608
Operation
Operation Timing of the WRn + Byte Control
Type .................................................. 204
Operation End
Operation End/Stopping ................................... 423
Operation Initialization Reset
Operation Initialization Reset (RST) .................... 95
Operation Initialization Reset (RST) Clear
Sequence.............................................. 98
Operation Initialization Reset (RST) State .......... 134
Operation Timing
Auto-refresh Operation Timing ......................... 227
Burst Read/Write Operation Timing .................. 225
Operation Timing for the CSn ->RD/WRn Setup and
RD/WRn ->CSn Hold Settings ............. 213
Operation Timing for DMA Fly-By Transfer
(I/O ->Memory).................................. 214
Operation Timing for DMA Fly-By Transfer
(Memory ->I/O).................................. 215
Operation Timing for Synchronous Write Enable
Output ............................................... 210
Operation Timing for the CSn Delay Setting ...... 212
Operation Timing of Read ->Write .................... 206
Single Read Operation Timing .......................... 226
Single Read/Write Operation Timing ......... 225, 226
Ordering
Bit Ordering ...................................................... 71
Byte Ordering.................................................... 71
Ordinary Bus Interface
Ordinary Bus Interface ..................................... 202
Oscillation Circuit
Quartz Oscillation Circuit ................................... 32
Oscillation Stabilization Wait
Oscillation Stabilization Wait Reset (RST)
Status................................................. 134
Oscillation Stabilization Wait RUN State ........... 134
Sources of an Oscillation Stabilization Wait ......... 99
Oscillation Stabilization Wait Time
Selecting an Oscillation Stabilization Wait
Time .................................................. 100
Other Instructions
Other Instructions ............................................ 589
Overview
Overview ........................................................ 450
P
PC
Program Counter (PC) ........................................ 63
PCNH
Bit Function of Control Status Registers
(PCNH,PCNL) ................................... 286
Control Status Registers (PCNH:PCNH3 to PCNH0,
PCNL:PCNL3 to PCNL0) ................... 286