Control/Status Registers A (Dmaca0 To Dmaca4) - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.2.1 Control/Status Registers A (DMACA0 to DMACA4)

Control/status registers A (DMACA0 to DMACA4) control the operation of the DMAC
channels. There is a separate register for each channel.
This section describes the configuration and functions of control/status registers A
(DMACA0 to DMACA4).
■ Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4)
Figure 14.2-2 shows the bit configuration of control/status registers A (DMACA0 to DMACA4).
Figure 14.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4)
bit 31
Address 000200 (ch.0)
H
DENB PAUS STRG
000208 (ch.1)
H
000210 (ch.2)
H
000218 (ch.3) bit 15
H
000220 (ch.4)
H
■ Detailed Bit of Control/Status Registers A (DMACA0 to DMACA4)
The following describes the functions of the bits of control/status registers A (DMACA0 to
DMACA4).
[bit31] DENB (Dma ENaBle): DMA operation enable bit
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.
The activated channel starts DMA transfer when a transfer request is generated and accepted.
All transfer requests that are generated for a deactivated channel are disabled.
When the transfer on an activated channel reaches the specified count, this bit is set to "0"
and transfer stops.
The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly
("0" write) only after temporarily stopping DMA using the PAUS bit (bit30 of DMACA). If the
transfer is forced to stop without first temporarily stopping DMA, DMA stops but the
transferred data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0]
bits [bit18 to bit16 of DMACB].
Table 14.2-1 shows the function of the DMA operation enable bit.
Table 14.2-1 Function of DMA Operation Enable Bit
DENB
0
1
• If a stop request is accepted during reset: Initialized to "0".
• This bit is readable and writable.
• If the operation of all channels is disabled by bit15 (DMAE bit) of the DMAC all-channel
control register (DMACR), writing "1" to this bit is disabled and the stopped state is
maintained. If the operation is disabled by the above bit while it is enabled by this bit, "0" is
written to this bit and the transfer is stopped (forced stop).
388
30 29 28 27 26 25 24
IS[4:0]
14 13 12 11 10 9
DTC[15:0]
Disables operation of DMA on the corresponding channel (initial value).
Enables operation of DMA on the corresponding channel.
23 22 21 20 19 18
DDNO[3:0] BLK[3:0]
8 7 6 5 4 3 2
Function
17 16 Initial value
00000000 0000XXXX
1 0
XXXXXXXX XXXXXXXX
B
B