Detailed On Registers Of The I C Interface - Fujitsu FR60 Hardware Manual

2
CHAPTER 16 I C INTERFACE
16.4 Detailed on Registers of the I
This section describes the detailed register of the I
■ Bus Status Register (IBSR0/IBSR1)
Address: 000095
This register is read only. All bits are cleared when the I
[bit7] BB (Bus Busy)
This bit indicates the status of the I
0
1
[bit6] RSC (Repeated Start Condition)
This bit is the repeated START condition detection bit.
0
1
This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition
is detected.
[bit5] AL (Arbitration Lost)
This bit is the arbitration lost detection bit.
0
1
Write "0" to the INT bit or "1" to the MSS bit of the IBCR register to clear this bit.
Arbitration lost is detected if:
• The transmission data does not match the data on the SDA line at the rising edge of SCL.
• A repeated START condition is generated in the first bit of the data by another master.
2
• The I
to "L" by another slave device.
[bit4] LRB (Last Received Bit)
This bit is an acknowledge storage bit that stores an acknowledge from the receiving device.
0
1
This bit is rewritten if an acknowledge is detected (reception 9 bits). This bit is cleared if a
START or STOP condition is detected.
454
bit 7
/0000B5
BB RSC
H H
R
Initial value=> 0
STOP condition detected
START condition detected (bus used)
Repeated START condition not detected
Repeated START condition detected while bus is being used
Arbitration lost not detected
Arbitration lost detected during master transmission
C interface cannot generate START or STOP condition because the SCL line is driven
Slave acknowledge detected
Slave acknowledge not detected
2
C Interface
2
C interface.
6 5 4 3
AL LRB TRX
R R R R
0 0 0 0
2
C stops operating (EN = 0 in ICCR).
2
C bus.
2 1 0
AAS GCA ADT
R R R
0 0 0