Fujitsu FR60 Hardware Manual page 231

CHAPTER 4 EXTERNAL BUS INTERFACE
• If synchronous write enable output is used, the following restrictions apply:
Do not set the following additional wait because the timing for synchronous write enable
output becomes meaningless:
- CS -> RD/WRn setup (Always write "0" to the W01 bit of AWR)
- First wait cycle setting (Always write "0000 " to bits W15 to W12 of AWR)
B
Do not set the following access types (TYP3 to TYP0 bits (bit3 to bit0) in the ACR register)
because the timing for synchronous write enable output becomes meaningless:
- Multiplex bus setting (Always write "0" to the TYP2 bit of ACR)
- RDY input enable setting (Always write "0" to the TYP0 bit of ACR)
Always set the burst length to "1" (BST1, BST0 bits = 0) for the synchronous write enable
output.
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