Occurrence Of Interrupts And Timing For Setting Flags - Fujitsu FR60 Hardware Manual

13.3.3 Occurrence of Interrupts and Timing for Setting Flags

The UART has five flags and two interrupt sources.
The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means
overrun error, and FRE means framing error. These flags are set when an error occurs
during reception and are then cleared when "0" is written to REC of the SCR register.
RDRF is set when receive data is loaded into the SIDR register and then cleared when
data is read from the SIDR register. Mode 1 does not provide a parity detection
function. Mode 2 does not provide a parity detection function and a framing error
detection function. TDRE is set when the SODR register is empty, and writing to it is
enabled and then cleared when data is written to the SODR register.
■ Occurrence of Interrupts and Timing for Setting Flags
There are two interrupt sources, one for receiving and the other for sending. During receiving,
an interrupt is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is
requested due to TDRE. The following shows the timing for setting the interrupt flags in each of
these modes.
❍ Receive operation in Mode 0
The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive
transfer is completed, causing an interrupt request to be generated for the CPU. The SIDR data
is invalid while PE, ORE, and FRE are active.
Figure 13.3-3 shows the timing for setting ORE, FRE, and RDRF in Mode 0.
Figure 13.3-3 Timing for Setting ORE, FRE, and RDRF (Mode 0)
PE,ORE,FRE
Receive interrupt
Data
D6
RDRF
D7 Stop
CHAPTER 13 UART
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