Fujitsu FR60 Hardware Manual page 23

■ Bus Interface
• Maximum operating frequency of 68 MHz (at using SDRAM)
• 24-bit address can be fully output (16-Mbyte space)
• 8-bit, 16-bit and 32-bit data I/O
• Prefetch buffer installed
• Unused data and address pins can be used as general-purpose I/O ports.
• Totally independent 8-area chip select output that can be defined at a minimum of 64K bytes
• Support of interfaces for various memory modules
- Asynchronous SRAM, asynchronous ROM/FLASH
- Page-mode ROM/FLASHROM (a page-size of 1, 2, 4, or 8 can be selected)
- Burst-mode ROM/FLASH (MBM29BL160D/161D/162D, etc.)
- SDRAM (or FCRAM type, CAS Latency1 to 8, 2/4 bank product)
- Address/data multiplexed bus (8-bit/16-bit width only)
• Basic bus cycle: 2 cycles
• Automatic wait cycle generator (Max 15 cycles) that can be programmed for each area and
can insert waits
• External wait cycles due to RDY input
• Endian setting of byte ordering (big/little) CS0 are, however, is only big endian
• Write disable setting (read only data)
• Enable/disable set of capturing to the built-in cache
• Enable/disable set of prefetch function
• Supports fly-by DMA transfer that enables independent I/O wait control
• External bus arbitration using BRQ and BGRNT is enabled
■ Built-in Memory
• DATA RAM: 4K bytes
• ROM: 4K bytes (MB91302A)
Built-in 8-Kbyte DATA RAM, 8-Kbyte DATA/instruction RAM and 8-Kbyte emulation RAM in
MB91V301A
■ Instruction Cache
• Capacity of 4K bytes
• 2 way set associative
• 128 block/way, 4 entry (4 words)/block
• Lock function allows specific program codes to stay resident in cache
• Instruction RAM function: A part of the instruction cache not in use can be used as RAM
■ DMAC (DMA Controller)
• 5 channels (2 channels for external to request)
• 3 transfer sources (external pins, internal peripherals, software)
CHAPTER 1 OVERVIEW
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