Fujitsu FR60 Hardware Manual page 72

CHAPTER 3 CPU AND CONTROL UNITS
■ Instruction Cache Tags
Figure 3.3-2 shows the configuration of the instruction cache tags.
Way 1
31
bit
Way 2
bit 31
The following describes the functions of the instruction cache tag bits.
[bit31 to bit9] Address tag
In the address tag, the high-order 23 bits of the memory address of an instruction cached in
a corresponding block are stored. The instruction data stored in Sub block k of Block i has
Memory Address IA, which is calculated as
IA = address-tag x 2
The address tag is used to check the matching of an instruction address requested for the
access by the CPU. Based on the result of the tag check, one of the following operations
occurs:
• If the requested instruction data exists in the cache (hit)
The data is transferred from the cache to the CPU within the cycle.
• If the requested instruction data does not exist in the cache (miss)
The data acquired via external access is acquired by the CPU and the cache simultaneously.
[bit7 to bit4] Sub block valid
If SBV3 to SBV0=1, the instruction data at the address indicated by the tag has been entered
in the corresponding sub block. Normally, two instructions can be stored in a sub block
(except for an immediate data transfer instruction).
[bit3] TAG valid bit
Indicates whether the address tag value is valid. If this bit is "0", the block becomes invalid
regardless of the sub block valid bit (when flushed).
[bit1] LRU (only for Way 1)
Exists only in the instruction cache tag of Way 1. Indicates whether, in a selected set, the
entry last accessed was Way 1 or Way 2. Indicates that the last accessed entry of the set
belongs to Way 1 if LRU=1 or Way 2 if LRU=0.
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Figure 3.3-2 Configuration of Instruction Cache Tags
Address tag
7
SBV3 SBV2
Address tag
7
SBV3 SBV2
9 4
+ i x 2 + k x 2
9 8
Blank
6 5 4 3
SBV1 SBV0 TAGV Empty LRU
9 8
Empty
6 5 4 3
SBV1 SBV0 TAGV
2
2 1 0
ETLK
2 1 0
Empty ETLK