2-Cycle Transfer (Sdram/Fcram -> I/O) - Fujitsu FR60 Hardware Manual

4.10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
This section describes the operation of 2-cycle transfer (SDRAM/FCRAM to I/O device).
■ 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
Figure 4.10-12 shows a timing chart for 2-cycle transfer (SDRAM/FCRAM to I/O).
Figure 4.10-12 Timing Chart for 2-cycle Transfer (SDRAM/FCRAM to I/O)
MCLK
A31 to A00
AS
CSn
RD
CSn
SRAS
SCAS
WRn(SWE)
D31 to D00
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
DREQn
• Bus access is the same as that of the interface for non-DMA transfer.
• In base mode, DACKn/DEOPn is output at both of transfer source bus access and transfer
destination bus access.
CHAPTER 4 EXTERNAL BUS INTERFACE
memory
address
I/O address
251