Fujitsu FR60 Hardware Manual page 451

■ Timing of the DEOP Pin Output
• The DEOP output of this DMA indicates that DMA transfer for the specified number of times
of the accepted channel has been completed.
• DEOP output is output when access to an external area of the last transfer block starts.
Thus, if any value other than "1" is set (block transfer mode) as the block size, DEOP is
output when the last data of the last block is transferred. In this case, the acceptance of the
next DREQ is already started even during transfer (before DEOP output) if the DACK pin
output is asserted.
• The DEOP output is synchronized with RD and WRn of external bus access timing.
However, if the transfer source/transfer destination is internal access, DEOP is not output.
To use DEOP output, it is necessary to enable the DEOP output using the port register.
■ If an External Pin Transfer Request is Re-entered during Transfer
❍ For burst, step, and block transfers
While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is
disabled. However, since operation of the external bus control unit and operation of the DMAC
are not completely synchronous, the circuit must be initialized to create DREQ pin input using
DACK and DEOP output to enable transfer requests by using DREQ input.
❍ For a demand transfer
If reloading of the transfer count register is specified when transfer for as many transfers as
specified has been completed, another transfer request is accepted.
■ If Another Transfer Request Occurs during Block Transfer
No request is detected before the transfer of the specified blocks is completed. At the block
boundaries, transfer requests accepted at that time are evaluated and then transfer on the
channel with the highest priority is performed.
■ Transfer between External I/O and External Memory
As targets of transfer by the DMAC, external I/O and external memory are not distinguished.
Specify an external I/O as a fixed external address.
To perform fly-by transfer, set the address of external memory in the transfer destination
address register. For external I/O, use DACK output and the signal decoded by the read signal
RD or write signal WRn pin.
■ AC Characteristics of DMAC
DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins
related to the DMAC. Output timing is synchronized with external bus access (refer to the AC
standard for the DMAC).
CHAPTER 14 DMA CONTROLLER (DMAC)
431