Fujitsu FR60 Hardware Manual page 398

CHAPTER 13 UART
❍ Receive operation in Mode 1
The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive
transfer is completed, causing an interrupt request to be generated for the CPU. The data
indicating an address or the data in last 9th bit is invalid because the length of data that can be
received is 8 bits. The SIDR data is invalid while ORE and FRE are active.
Figure 13.3-4 shows the timing for setting ORE, FRE, and RDRF in Mode 1.
Figure 13.3-4 Timing for Setting ORE, FRE, and RDRF (Mode 1)
Receive interrupt
❍ Reception operation in Mode 2
The ORE and RDRF flags are set when the last data (D7) is set after the reception transfer is
completed, generating an interrupt request to the CPU. The SIDR data is invalid while ORE is
active.
Figure 13.3-5 shows the timing of setting ORE and RDRF in Mode 2.
Receive interrupt
378
Data D7
ORE,FRE
RDRF
Figure 13.3-5 Timing of Setting ORE and RDRF (Mode 2)
Data
D5
ORE
RDRF
Address/data Stop
D6 D7