Pin/Timing Control Register (Tcr) - Fujitsu FR60 Hardware Manual

4.2.9

Pin/Timing Control Register (TCR)

This section explains the configuration and functions of the pin/timing control register
and its function.
■ Configuration of the Pin/Timing Control Register (TCR)
The pin/timing control register (TCR: Terminal and Timiting Control Register) controls the
functions related to the general external bus interface controller, such as the setting of common
pin functions and timing control.
Figure 4.2-9 shows the configuration of the pin/timing control register (TCR).
Figure 4.2-9 Configuration of the Pin/Timing Control Register (TCR)
Address bit 7
000683
BREN
H
■ Functions of Bits in the Pin/Timing Control Register (TCR)
The following explains the functions of the bits in the pin/timing control register (TCR).
[bit7] BREN (BRQ Enable)
This bit enables BRQ pin input and external bus sharing.
Table 4.2-38 BRQ input enable setting
BREN
0
1
In the initial state ("0"), BRQ input is ignored. When "1" is set, the bus is made open (control
with high impedance) and BGRNT is activated ("L" level is output) when the bus is ready to be
made open after the BRQ input becomes "H" level.
[bit6] PSUS (Prefetch suspend)
This bit controls temporary stopping of prefetch to all areas.
Table 4.2-39 Function of prefetch control
PSUS
0
1
If "1" is set, no new prefetch operation is performed before "0" is written. Since during this time
the contents of the prefetch buffer are not deleted unless a prefetch buffer occurs, clear the
prefetch buffer using the PCLR bit function (bit5) before restarting prefetch.
6 5 4
PSUS PCLR Reserved OHT1
No bus sharing by BRQ/BGRNT. BRQ input is disabled.
Bus sharing by BRQ/BGRNT. BRQ input is enabled.
CHAPTER 4 EXTERNAL BUS INTERFACE
3 2 1
OHT0 RDW1 RDW0
BRQ input enable setting
Prefetch control
Enable prefetch
Suspend prefetch
0 Initial value
00000000 (INIT)
B
0000XXXX (RST)
B
Access
R/W
175