Block Diagram Of Clock Generation Section - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.7.1

Block Diagram of Clock Generation Section

The clock generation section consists of the following five blocks:
• Oscillation clock generator/sub clock generator
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
I Block Diagram of Clock Generation Section
Figure 3.7-2 shows the block diagram of the clock generation section. It also includes the standby
controller and timebase timer circuit.
Reset
Interrupt
X0 Pin
X1 Pin
X0A Pin
X1A Pin
S Set
R Reset
Q Output
110
Figure 3.7-2 Block Diagram of Clock Generation Section
Standby control cicuit
Low-power Consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
S Q
R
S Q
R
Operation clock
selector
PLL multiplying
circuit
2-
frequency
division
Oscillation
Main
clock
clock
Oscillation clock
Sub clock
generator (HCLK)
4-frequency
division
Sub clock generator
CPUintermittent
Re-
operation cycle
served
selector
2
Clock mode
Sleep signal
Stop signal
S Q
Machine
R
S Q
R
2
2
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
1024- 2- 4- 2-
frequency frequency frequency frequency frequency
division division division division
Timebase timer
8-
1024-frequency
frequency
division
division
Watch timer
CPU clock
CPU
control circuit
operation
clock
Peripheral clock
Peripheral
control circuit
function
operation clock
clock
Oscillation
stabilization
wait time selector
2- 2- 2- 2-
frequency frequency frequency
division division division division
To watchdog timer
2- 2-
frequency frequency
division division