Fujitsu FR60 Hardware Manual page 491

32-bit microcontroller mb91301 series
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❍ Communication Error that Causes No Errors
If, during transmission in master mode, an illegal clock is generated on the SCL line due to
noise or for some other reason, the transmission bit counter of the I
causing the slave to hang while L has appeared on the SDA line in the ACK cycle.
An error (AL=1, BER=1) does not occur for such an illegal clock.
If this situation occurs, perform the following error processing:
1. A communication error can be assumed if LRB=1 when MSS=1, TRX=1, INT=1.
2. Set EN to "0" and then set EN to "1" to cause SCL to generate one clock on a pseudo basis.
This action causes the slave to release the bus. The period from the time EN is set to "0"
until EN is set to "1" must be long enough for the slave to recognize it as a clock (about as
long as the H period of a transmission clock).
3. Since the IBSR and IBCR are cleared when EN is set to "0", perform retransmission
processing from the START condition. No STOP condition is generated at this point if BSS is
set to "0". Insert an interval equal to or longer than n x 7 x t
EN is set to "1" and the point at which MSS is set to "1" (START condition).
Example:
High-speed mode: 6 x 7 x 30.3=about 1.273 µs
Standard mode: 27 x 7 x 30.3=about 5.727 µs
Note:
Since BER, if set, is not cleared even if EN is set to "0", first clear it and then resend it.
2
CHAPTER 16 I
C INTERFACE
2
C interface may run quickly,
between the point at which
CPP
471

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