Fujitsu FR60 Hardware Manual page 84

CHAPTER 3 CPU AND CONTROL UNITS
■ Table Base Register (TBR)
This section describes the functions of the table base register (TBR: Table Base Register).
The table base register (TBR) consists of 32 bits. Figure 3.4-3 shows the configuration of table
base register (TBR) bit.
TBR
The table base register holds the first address of the vector table to be used during EIT
processing.
The initial value upon reset is 000FFC00
■ Return Pointer (RP)
This section describes the functions of the return pointer (RP: Return Pointer).
The return pointer (RP) consists of 32 bits. Figure 3.4-4 shows the configuration of return pointer
(RP) bit.
RP
The return pointer holds the return address from a subroutine.
When the CALL instruction is executed, the value of the PC is transferred to the RP.
When the RET instruction is executed, the contents of the RP are transferred to the PC.
The initial value upon reset is undefined.
■ System Stack Pointer (SSP)
This section describes the functions of the system stack pointer (SSP: System Stack Pointer).
The system stack pointer (SSP) consists of 32 bits. Figure 3.4-5 shows the configuration of system
stack pointer (SSP) bit.
SSP
The SSP is the system stack pointer.
This register is used as an R15 general-purpose register if the S flag of the condition code
register (CCR) is "0".
The SSP can also be specified explicitly.
This register is also used as a stack pointer that specifies a stack on which the contents of the
PS and PC are to be saved if an EIT occurs.
The initial value upon reset is 00000000
64
Figure 3.4-3 Configuration of Table Base Register Bit
bit31
Figure 3.4-4 Configuration of Return Pointer Bit
bit31
Figure 3.4-5 Configuration of System Stack Pointer Bit
bit31
bit0
.
H
bit0
bit0
.
H
[Initial value]
000FFC00
H
[Initial value]
XXXXXXXX
H
[Initial value]
00000000
H