Dma Fly-By Transfer (I/O -> Memory) - Fujitsu FR60 Hardware Manual

4.10.1 DMA Fly-By Transfer (I/O -> Memory)
This section explains DMA fly-by transfer (I/O -> memory).
■ DMA Fly-By Transfer (I/O -> Memory)
Figure 4.10-1 shows the operation timing chart for (TYP3 to TYP0=0000
IOWR=41
Figure 4.10-1 shows a case when a wait is not set on the memory side.
Figure 4.10-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)
MCLK
A31 to A00
AS
CSn
WRn
D31 to D00
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
IORD
DREQn
• Setting "1" for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to
be set. Set this bit to extend the period between assertion of chip select and the read/write
strobe.
• Setting "1" for the W00 bit of the AWR register enables the RD/WRn -> CSn hold delay to be
set. Set this bit to extend the period between negation of the read/write strobe and negation
of chip select.
).
H
Basic cycle
CHAPTER 4 EXTERNAL BUS INTERFACE
I/O wait I/O hold
cycle wait
memory address
, AWR=0008
B
Sense timing in
demand mode
237
,
H