Page 1 FUJITSU SEMICONDUCTOR CM71-00101-5E CONTROLLER MANUAL FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL...
Page 3 FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL FUJITSU LIMITED...
Page 5 Also, for the rules of assembly language grammar and the use of assembler programs, refer to the "FR Family Assembler Manual". * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Page 6 ■ Organization of this manual This manual consists of the following 7 chapters and 1 appendix: CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU.
Page 7 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 FR FAMILY OVERVIEW ................1 Features of the FR Family CPU Core ....................2 Sample Configuration of an FR Family Device ................... 3 Sample Configuration of the FR Family CPU ..................4 CHAPTER 2 MEMORY ARCHITECTURE ................ 5 FR Family Memory Space ........................
Page 10 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ..... 53 Pipeline Operation ..........................54 Pipeline Operation and Interrupt Processing ..................55 Register Hazards ..........................56 Delayed Branching Processing ......................58 5.4.1 Processing Non-delayed Branching Instructions ................. 60 5.4.2 Processing Delayed Branching Instructions ................61 CHAPTER 6 INSTRUCTION OVERVIEW ...............
Page 11 7.35 MULU (Multiply Unsigned Word Data) .................... 122 7.36 MULH (Multiply Half-word Data) ..................... 124 7.37 MULUH (Multiply Unsigned Half-word Data) .................. 126 7.38 DIV0S (Initial Setting Up for Signed Division) ................. 128 7.39 DIV0U (Initial Setting Up for Unsigned Division) ................130 7.40 DIV1 (Main Process of Division) .....................
Page 12 7.82 MOV (Move Word Data in Source Register to Destination Register) ..........178 7.83 MOV (Move Word Data in Source Register to Destination Register) ..........179 7.84 MOV (Move Word Data in Program Status Register to Destination Register) ........ 180 7.85 MOV (Move Word Data in Source Register to Destination Register) ..........
Page 13 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ............240 7.124 ADDSP (Add Stack Pointer and Immediate Data) ................241 7.125 EXTSB (Sign Extend from Byte Data to Word Data) ..............242 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) ..............243 7.127 EXTSH (Sign Extend from Byte Data to Word Data) ..............
Page 15 Main changes in this edition Page Changes (For details, refer to main body.) Be sure to refer to the "Check Sheet" for the latest cautions on development. is changed. ("Check Sheet" is seen at the following support page... is deleted.) "■...
Page 16 Page Changes (For details, refer to main body.) "4.3.1 User Interrupts" is changed. ( "External" → "User" ), ( "external" → "user" ) "■ Overview of User Interrupts" is changed. ( "External" → "User" ) "■ Overview of User Interrupts" is changed. ( "Interrupts are referred to as "external"...
Page 17 Page Changes (For details, refer to main body.) "7.15 AND (And Word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0100 0010 0011" is added.) "7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0101 0010 0011"...
Page 18 Page Changes (For details, refer to main body.) "7.42 DIV3 (Correction when Remainder is 0)" is changed. ( "Instruction bit pattern : 1001 1111 0110 0000" is added. ) "7.43 DIV4S (Correction Answer for Signed Division)" is changed. ( "Instruction bit pattern : 1001 1111 0111 0000" is added. ) "7.44 LSL (Logical Shift to the Left Direction)"...
Page 19 Page Changes (For details, refer to main body.) "7.67 LDUB (Load Byte Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0010 0010 0011" is added. ) "7.69 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0100 0010 0011"...
Page 20 Page Changes (For details, refer to main body.) "7.88 CALL (Call Subroutine)" is changed. ( "extension for use as the branch destination address" → "extension" ) "7.88 CALL (Call Subroutine)" is changed. ( "CALL 120H" → " CALL label label: ; CALL instruction address + 122 "...
Page 21 Page Changes (For details, refer to main body.) "7.96 CALL:D (Call Subroutine)" is changed. ( "CALL : D 120H LDI : 8 #0, R2 ; Instruction placed in delay slot" → "CALL:D label LDI : 8 #0, R2 ; Instruction placed in delay slot label: ;...
Page 22 Page Changes (For details, refer to main body.) "7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1000 0011 1111 1110" is added. ) "7.122 ORCCR (Or Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1001 0011 0001 0000"...
Page 23 Page Changes (For details, refer to main body.) "A.1 Symbols Used in Instruction Lists" is chenged. ● Symbols in Mnemonic and Operation Columns is changed. i8 .....( "128 to 255" → "0 to 255" ) "A.1 Symbols Used in Instruction Lists" is chenged. ●...
Page 24 Page Changes (For details, refer to main body.) "Table A.2-6 Shift Instructions (9 Instructions)" is changed. ( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} → Ri" ) ( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" ) ( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" ) "Table A.2-13 Direct Addressing Instructions (14 Instructions)"...
Page 25: Chapter 1 Fr Family Overview
CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. 1.1 Features of the FR Family CPU Core 1.2 Sample Configuration of an FR Family Device 1.3 Sample Configuration of the FR Family CPU...
Page 26: Features Of The Fr Family Cpu Core
CHAPTER 1 FR FAMILY OVERVIEW Features of the FR Family CPU Core The FR family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit "RISC" based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required.
Page 27: Sample Configuration Of An Fr Family Device
CHAPTER 1 FR FAMILY OVERVIEW Sample Configuration of an FR Family Device FR family devices have block configuration with bus connections between individual modules. This enables module connections to be altered as necessary to accommodate a wide variety of functional configurations. Figure 1.2-1 shows an example of the configuration of an FR family device.
Page 28: Sample Configuration Of The Fr Family Cpu
CHAPTER 1 FR FAMILY OVERVIEW Sample Configuration of the FR Family CPU The FR family CPU core features a block configuration organized around general- purpose registers, with dedicated registers, "ALU" units, multipliers and other features included for each specific application. Figure 1.3-1 shows a sample configuration of an FR family CPU.
Page 29: Chapter 2 Memory Architecture
CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU. Memory architecture includes the allocation of memory space as well as methods used to access memory. 2.1 FR Family Memory Space 2.2 Bit Order and Byte Order 2.3 Word Alignment...
Page 30: Fr Family Memory Space
CHAPTER 2 MEMORY ARCHITECTURE FR Family Memory Space The FR family controls memory space in byte units, and provides linear designation of 32-bit spaces. Also, to enhance instruction efficiency, specific areas of memory are allocated for use as direct address areas and vector table areas. ■...
Page 31: Direct Address Area
CHAPTER 2 MEMORY ARCHITECTURE 2.1.1 Direct Address Area The lower portion of the address space is used for the direct address area. Instructions that specify direct addresses allow you to access this area without the use of general- purpose registers, using only the operand information in the instruction itself. The size of the address area that can be specified by direct addressing varies according to the length of the data being transferred.
Page 32: Vector Table Area
CHAPTER 2 MEMORY ARCHITECTURE 2.1.2 Vector Table Area An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT" vector addresses. ■ Overview of Vector Table Areas An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT" vector addresses.
Page 33: Contents Of Vector Table Areas
CHAPTER 2 MEMORY ARCHITECTURE ■ Contents of Vector Table Areas A vector table is composed of entry addresses for each of the "EIT" processing programs. Each table contains some values whose use is fixed according to the CPU architecture, and some that vary according to the types of built-in peripheral circuits present.
Page 34: Bit Order And Byte Order
CHAPTER 2 MEMORY ARCHITECTURE Bit Order and Byte Order This section describes the order in which three types of data, 8, 16, and 32 bits, are placed in the memory in the FR family. In the FR family, the bit number increases approaching the MSB, and the byte number increases approaching the lowest address value.
Page 35: Word Alignment
CHAPTER 2 MEMORY ARCHITECTURE Word Alignment In the FR family, the type of data length used determines restrictions on the designation of memory addresses (word alignment). ■ Program Restrictions on Word Alignment When using half-word instruction length, memory addresses must be accessed in multiples of two. With branching instructions and other instructions that may result in attempting to store odd numbered values to the "PC", the lowest value in the "PC"...
Page 36 CHAPTER 2 MEMORY ARCHITECTURE...
Page 37: Chapter 3 Register Descriptions
CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU. 3.1 FR Family Register Configuration 3.2 General-purpose Registers 3.3 Dedicated Registers...
Page 38: Fr Family Register Configuration
CHAPTER 3 REGISTER DESCRIPTIONS FR Family Register Configuration FR family devices use two types of registers, general-purpose registers and dedicated registers. • General-purpose registers: Store computation data and address information • Dedicated registers: Store information for specific applications Figure 3.1-1 shows the configuration of registers in FR family devices. ■...
Page 39: General-Purpose Registers
CHAPTER 3 REGISTER DESCRIPTIONS General-purpose Registers The FR family CPU uses general-purpose registers to hold the results of various calculations, as well as information about addresses to be used as pointers for memory access. These registers also have special functions with certain types of instructions. ■...
Page 40 CHAPTER 3 REGISTER DESCRIPTIONS ● R14 (Frame Pointer: FP) • Index register for load/store to memory instructions [Example: LD @(R14, disp10), Ri] • Frame pointer for reserve/release of dynamic memory area [Example: ENTER #u10] ● R15 (Stack Pointer: SP) • Index register for load/store to memory instructions [Example: LD @(R15, udisp6), Ri] •...
Page 41: Dedicated Registers
CHAPTER 3 REGISTER DESCRIPTIONS Dedicated Registers The FR family has six 32-bit registers reserved for various special purposes, plus one 64-bit dedicated register for multiplication and division operations. ■ Dedicated Registers The following seven dedicated registers are provided. For details, see the descriptions in Sections "3.3.1 Program Counter (PC)"...
Page 42: Program Counter (Pc)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.1 Program Counter (PC) This register indicates the address containing the instruction that is currently executing. Following a reset, the contents of the PC are set to the reset entry address contained in the vector table. ■...
Page 43: Program Status (Ps)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.2 Program Status (PS) The program status (PS) indicates the status of program execution, and consists of the following three parts: • Interrupt level mask register (ILM) • System condition code register (SCR) • Condition code register (CCR) ■...
Page 44 CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-4 "ILM" Register Functions FR family CPU I flag Interrupt controller Interrupt activated Interrupt Peripheral Comp 29>25 request Activation OK ● Range of ILM Program Setting Values If the original value of the register is in the range 16 to 31, the new value may be set in the range 16 to 31. If an instruction attempts to set a value between 0 and 15, that value will be converted to "setting value + 16"...
Page 45 CHAPTER 3 REGISTER DESCRIPTIONS ■ Condition Code Register (CCR: Bit 07 to bit 00) ● Bit Configuration of the "CCR" Figure 3.3-6 Bit Configuration of the "CCR" Initial value: --00XXXX ● "CCR" Functions • "S" Flag This flag selects the stack pointer to be used. The value "0" selects the system stack pointer (SSP), and "1"...
Page 46 CHAPTER 3 REGISTER DESCRIPTIONS ■ Note on PS Register Because of prior processing of the PS register by some commands, a break may be brought in an interrupt processing subroutine during the use of a debugger or flag display content in the PS register may be changed with the following exceptional operations.
Page 47: Table Base Register (Tbr)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.3 Table Base Register (TBR) The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. ■ Overview of the Table Base Register The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. When an "EIT"...
Page 48: Table Base Register Configuration
CHAPTER 3 REGISTER DESCRIPTIONS ■ Table Base Register Configuration Figure 3.3-8 shows the bit configuration of the table base register. Figure 3.3-8 Table Base Register Bit Configuration Bit no. ■ Table Base Register Functions ● Vector Table Reference Addresses Addresses for vector reference are generated by adding the contents of the "TBR" register and the vector offset value, which is determined by the type of interrupt used.
Page 49: Return Pointer (Rp)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.4 Return Pointer (RP) The return pointer (RP) is a register used to contain the program counter (PC) value during execution of call instructions, in order to assure return to the correct address after the call instruction has executed. ■...
Page 50 CHAPTER 3 REGISTER DESCRIPTIONS ■ Return Pointer Configuration Figure 3.3-11 shows the bit configuration of the return pointer. Figure 3.3-11 Return Pointer Bit Configuration Bit no. ■ Return Pointer Functions ● Return Pointer in Multiple "CALL" Instructions Because the "RP" does not have a stack configuration, it is necessary to first execute a save when calling one subroutine from another subroutine.
Page 51: System Stack Pointer (Ssp), User Stack Pointer (Usp)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) The system stack pointer (SSP) and user stack pointer (USP) are registers that refer to the stack area. The "S" flag in the "CCR" determines whether the "SSP" or "USP" is used.
Page 52 CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15" when "S" Flag = 1 Before execution of ST R13,@-R15 After execution of ST R13,@-R15 Memory space Memory space 00000000 00000000 ???????? 12345678 12345678 17263540...
Page 53: Multiplication/Division Register (Md)
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.6 Multiplication/Division Register (MD) The multiplication/division register (MD) is a 64-bit register used to contain the result of multiplication operations, as well as the dividend and result of division operations. ■ Overview of the Multiplication/Division Register The multiplication/division register (MD) is a register used to contain the result of multiplication operations, as well as the dividend and result of division operations.
Page 54 CHAPTER 3 REGISTER DESCRIPTIONS ■ Configuration of the "MD" Register Figure 3.3-17 shows the bit configuration of the "MD". Figure 3.3-17 Bit Configuration of the "MD" Bit no. ■ Functions of the "MD" ● Storing Results of Multiplication and Division The results of multiplication operations are stored in the "MDH"...
Page 55: Chapter 4 Reset And "Eit" Processing
CHAPTER 4 RESET AND "EIT" PROCESSING This chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning. "EIT" processing, in contrast, terminates the currently executing process and saves restart information to the memory, then transfers control to a predetermined...
Page 56 CHAPTER 4 RESET AND "EIT" PROCESSING 4.1 Reset Processing 4.2 Basic Operations in "EIT" Processing 4.3 Interrupts 4.4 Exception Processing 4.5 Traps 4.6 Priority Levels...
Page 57: Reset Processing
CHAPTER 4 RESET AND "EIT" PROCESSING Reset Processing A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning. Resets are used to start the LSI operating from its initial state, as well as to recover from error conditions. ■...
Page 58: Basic Operations In "Eit" Processing
CHAPTER 4 RESET AND "EIT" PROCESSING Basic Operations in "EIT" Processing Interrupts, exceptions and traps are similar operations applied under partially differing conditions. Each "EIT" event involves terminating the execution of instructions, saving information for restarting, and branching to a designated processing program. ■...
Page 59: Vector Table Configuration
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Vector Table Configuration Vector tables are located in the main memory, occupying an area of 1 Kbyte beginning with the address shown in the TBR. These areas are intended for use as a table of entry addresses for "EIT" processing, however in applications where vector tables are not required, this area can be used as a normal instruction or data area.
Page 60 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saved Registers Except in the case of reset processing, the values of the "PS" and "PC" are saved to the stack as designated by the "SSP", regardless of the value of the "S" flag in the "CCR". No save operation is used in reset processing.
Page 61: Interrupts
CHAPTER 4 RESET AND "EIT" PROCESSING Interrupts Interrupts originate independently of the instruction sequence. They are processed by saving the necessary information to resume the currently executing instruction sequence, and then starting the processing routine corresponding to the type of interrupt that has occurred.
Page 62: User Interrupts
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3.1 User Interrupts User interrupts originate as requests from peripheral circuits. Each interrupt request is assigned an interrupt level, and it is possible to mask requests according to their level values. This section describes conditions for acceptance of user interrupts, as well as their operation and uses.
Page 63: How To Use User Interrupts
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Time to Start of Interrupt Processing The time required to start interrupt processing can be expressed as a maximum of "n + 6" cycles from the start of the instruction currently executing when the interrupt was received, where "n" represents the number of execution cycles in the instruction.
Page 64: Non-Maskable Interrupts (Nmi)
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3.2 Non-maskable Interrupts (NMI) Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests can be produced when "NMI" external signal pin input to the microcontroller is active. This section describes conditions for the acceptance of "NMI" interrupts, as well as their operation and uses.
Page 65 CHAPTER 4 RESET AND "EIT" PROCESSING ■ "PC" Values Saved for Non-maskable Interrupts When an "NMI" is accepted by the processor, those instructions in the pipeline that cannot be interrupted in time will be executed. The remainder of the instructions will be canceled, and will not be processed after the interrupt.
Page 66: Exception Processing
CHAPTER 4 RESET AND "EIT" PROCESSING Exception Processing Exceptions originate from within the instruction sequence. Exceptions are processed by first saving the necessary information to resume the currently executing instruction, and then starting the processing routine corresponding to the type of exception that has occurred.
Page 67: Undefined Instruction Exceptions
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4.1 Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined. This section describes the operation, time requirements and uses of undefined- instruction exceptions. ■ Overview of Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined.
Page 68: Traps
CHAPTER 4 RESET AND "EIT" PROCESSING Traps Traps originate from within the instruction sequence. Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence, and then starting the processing routine corresponding to the type of trap that has occurred.
Page 69: Int" Instructions
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.1 "INT" Instructions The "INT" instruction is used to create a software trap. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INT" instruction. ■ Overview of the "INT" Instruction The "INT #u8"...
Page 70: Inte" Instruction
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.2 "INTE" Instruction The "INTE" instruction is used to create a software trap for debugging. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INTE" instruction. ■...
Page 71: Step Trace Traps
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.3 Step Trace Traps Step trace traps are traps used by debuggers. This type of trap can be created for each individual instruction in a sequence by setting the "T" flag in the system condition code register (SCR) in the program status (PS).
Page 72: Coprocessor Not Found Traps
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.4 Coprocessor Not Found Traps Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not found in the system. This section describes conditions for the generation of coprocessor not found traps, in addition to operation, program counter (PC) values saved, and other information.
Page 73: Coprocessor Error Trap
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.5 Coprocessor Error Trap A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU executes another coprocessor instruction involving the same coprocessor. This section describes conditions for the generation, operations, and program counter (PC) values saved of coprocessor error traps.
Page 74 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saving and Restoring Coprocessor Error Information When a coprocessor is used in a multi-tasking environment, the internal resources of the coprocessor become part of the system context. Thus whenever context switching occurs, it is necessary to save or restore the contents of the coprocessor.
Page 75: Priority Levels
CHAPTER 4 RESET AND "EIT" PROCESSING Priority Levels When multiple "EIT" requests occur at the same time, priority levels are used to select one source and execute the corresponding "EIT" sequence. After the "EIT" sequence is completed, "EIT" request detection is applied again to enable processing of multiple "EIT"...
Page 76 CHAPTER 4 RESET AND "EIT" PROCESSING ■ Priority of Multiple Processes When the acceptance of an "EIT" source results in the masking of other sources, the priority of execution of simultaneously occurring "EIT" handlers is as shown in Table 4.6-2. Table 4.6-2 Priority of Execution of "EIT"...
Page 77: Chapter 5 Precautionary Information For The Fr Family Cpu
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU. 5.1 Pipeline Operation 5.2 Pipeline Operation and Interrupt Processing 5.3 Register Hazards 5.4 Delayed Branching Processing...
Page 78: Pipeline Operation
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Pipeline Operation The FR family CPU processes all instructions using a 5-stage pipeline operation. This makes it possible to process nearly all instructions within one cycle. ■ Overview of Pipeline Operation In a pipeline operation the steps by which the CPU interprets and executes instructions are divided into several cycles, so that instructions can be processed simultaneously in successive cycles.
Page 79: Pipeline Operation And Interrupt Processing
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Pipeline Operation and Interrupt Processing The FR family CPU processes all instructions through pipeline operation. Therefore, particularly for instructions that start hardware events, it is possible for contradictory conditions to exist before and after an instruction. ■...
Page 80: Register Hazards
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Register Hazards The FR family CPU executes program steps in the order in which they are written, and is therefore equipped with a function that detects the occurrence of register hazards and stops pipeline processing when necessary.
Page 81 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ■ Interlocking Instructions which are relatively slow in loading data to the CPU may cause register hazards that cannot be handled by register bypassing. In the example in Figure 5.3-3, data required for the "ID" stage of the "SUB" instruction must be loaded to the CPU in the "MA"...
Page 82: Delayed Branching Processing
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Delayed Branching Processing Because the FR family CPU features pipeline operation, branching instructions must first be loaded before they are executed. Delayed branching processing is the function to execute the loaded instruction, and allows to accelerate processing speeds. ■...
Page 83 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU • AND Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri EORH Rj, @Ri EORB Rj, @Ri • BANDH #u4, @Ri BANDL #u4, @Ri BORH #u4, @Ri BORL...
Page 84: Processing Non-Delayed Branching Instructions
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.4.1 Processing Non-delayed Branching Instructions The FR family CPU processes non-delayed branching instructions in the order in which the program is written, introducing a 1-cycle delay in execution speed if branching takes place. ■...
Page 85: Processing Delayed Branching Instructions
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.4.2 Processing Delayed Branching Instructions The FR family CPU processes delayed branching instructions with an apparent execution speed of 1 cycle, regardless of whether branching conditions are satisfied or not satisfied. When branching occurs, this is one cycle faster than using non-delayed branching instructions.
Page 86 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ■ Examples of Programing Delayed Branching Instructions An example of programing a delayed branching instruction is shown below. @R10, R1 @R11, R2 R1, R3 BNE:D TestOK R2, @R12 #4, R12 ; not satisfy TestOK: ;...
Page 87: Chapter 6 Instruction Overview
CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR family CPU. All FR family CPU instructions are in 16-bit fixed length format, except for immediate data transfer instructions which may exceed 16 bits in length. This format enables the creation of a compact object code and smoother pipeline processing.
Page 88: Instruction Formats
CHAPTER 6 INSTRUCTION OVERVIEW Instruction Formats The FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. ■ Instruction Formats All instructions used by the FR family CPU are written in the six formats shown in Figure 6.1-1. Figure 6.1-1 Instruction Formats 16bits 8bits...
Page 89 CHAPTER 6 INSTRUCTION OVERVIEW ■ Relation between Bit Pattern "Rs" and Register Values Table 6.1-2 shows the relation between dedicated register numbers and field bit pattern values. Table 6.1-2 Dedicated Register Numbers and Field Bit Pattern Values Register Register Register Register 0000 0100...
Page 90: Instruction Notation Formats
CHAPTER 6 INSTRUCTION OVERVIEW Instruction Notation Formats FR family CPU instructions are written in the following three notation formats. • Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results stored at operand 2. •...
Page 91: Chapter 7 Detailed Execution Instructions
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter presents each of the execution instructions used by the FR family assembler, in reference format. The execution instructions used by the FR family CPU are classified as follows. • Add/Subtract Instructions • Compare Instructions •...
Page 92: Chapter 7 Detailed Execution Instructions
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ADDN (Add Word Data of Source Register to Destination Register) ADDN (Add Immediate Data to Destination Register) ADDN2 (Add Immediate Data to Destination Register) SUB (Subtract Word Data in Source Register from Destination Register) SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)
Page 93 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) 7.41 DIV2 (Correction when Remainder is 0) 7.42 DIV3 (Correction when Remainder is 0) 7.43 DIV4S (Correction Answer for Signed Division) 7.44 LSL (Logical Shift to the Left Direction) 7.45 LSL (Logical Shift to the Left Direction) 7.46...
Page 94 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) 7.78 STH (Store Half-word Data in Register to Memory) 7.79 STB (Store Byte Data in Register to Memory) 7.80 STB (Store Byte Data in Register to Memory) 7.81 STB (Store Byte Data in Register to Memory) 7.82...
Page 95 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) 7.111 DMOVB (Move Byte Data from Register to Direct Address) 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) 7.114 LDRES (Load Word Data in Memory to Resource) 7.115 STRES (Store Word Data in Resource to Memory)
Page 96: Add (Add Word Data Of Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD (Add Word Data of Source Register to Destination Register) Adds word data in "Rj" to word data in "Ri", stores results to "Ri". ■ ADD (Add Word Data of Source Register to Destination Register) Assembler format: ADD Rj, Ri Ri + Rj →...
Page 97: Add (Add 4-Bit Immediate Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD (Add 4-bit Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", stores results to the "Ri". ■ ADD (Add 4-bit Immediate Data to Destination Register) Assembler format: ADD #i4, Ri Ri + extu(i4) →...
Page 98: Add2 (Add 4-Bit Immediate Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADD2 (Add 4-bit Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to the word data in "Ri", stores results to "Ri". The way a "C" flag of this instruction varies is the same as the ADD instruction ; it is different from that of the SUB instruction.
Page 99: Addc (Add Word Data Of Source Register And Carry Bit To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Adds the word data in "Rj" to the word data in "Ri" and carry bit, stores results to "Ri". ■ ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Assembler format: ADDC Rj, Ri Ri + Rj + C →...
Page 100: Addn (Add Word Data Of Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN (Add Word Data of Source Register to Destination Register) Adds the word data in "Rj" and the word data in "Ri", stores results to "Ri" without changing flag settings. ■ ADDN (Add Word Data of Source Register to Destination Register) Assembler format: ADDN Rj, Ri Ri + Rj →...
Page 101: Addn (Add Immediate Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", stores the results to "Ri" without changing flag settings. ■...
Page 102: Addn2 (Add Immediate Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ADDN2 (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to word data in "Ri", stores the results to "Ri" without changing flag settings. ■...
Page 103: Sub (Subtract Word Data In Source Register From Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS SUB (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri". ■ SUB (Subtract Word Data in Source Register from Destination Register) Assembler format: SUB Rj, Ri Ri –...
Page 104: Subc (Subtract Word Data In Source Register And Carry Bit From Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores results to "Ri". ■ SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Assembler format: SUBC Rj, Ri...
Page 105: Subn (Subtract Word Data In Source Register From Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.10 SUBN (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri" without changing the flag settings. ■ SUBN (Subtract Word Data in Source Register from Destination Register) Assembler format: SUBN Rj, Ri Ri –...
Page 106: Cmp (Compare Word Data In Source Register And Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.11 CMP (Compare Word Data in Source Register and Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", places results in the condition code register (CCR). ■ CMP (Compare Word Data in Source Register and Destination Register) Assembler format: CMP Rj, Ri Operation:...
Page 107: Cmp (Compare Immediate Data Of Source Register And Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.12 CMP (Compare Immediate Data of Source Register and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension from the word data in "Ri", places results in the condition code register (CCR). ■...
Page 108: Cmp2 (Compare Immediate Data And Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.13 CMP2 (Compare Immediate Data and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate(from -16 to -1) data with minus extension from the word data in "Ri", places results in the condition code register (CCR).
Page 109: And (And Word Data Of Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.14 AND (And Word Data of Source Register to Destination Register) Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the results to "Ri". ■ AND (And Word Data of Source Register to Destination Register) Assembler format: AND Rj, Ri Ri and Rj →...
Page 110: And (And Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.15 AND (And Word Data of Source Register to Data in Memory) Takes the logical AND of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 111 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: AND R2, @R3 Instruction bit pattern : 1000 0100 0010 0011 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 112: Andh (And Half-Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.16 ANDH (And Half-word Data of Source Register to Data in Memory) Takes the logical AND of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 113 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDH R2, @R3 Instruction bit pattern : 1000 0101 0010 0011 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 114: Andb (And Byte Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.17 ANDB (And Byte Data of Source Register to Data in Memory) Takes the logical AND of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 115 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDB R2, @R3 Instruction bit pattern : 1000 0110 0010 0011 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 116: Or (Or Word Data Of Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.18 OR (Or Word Data of Source Register to Destination Register) Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the results to "Ri". ■ OR (Or Word Data of Source Register to Destination Register) Assembler format: OR Rj, Ri Ri or Rj →...
Page 117: Or (Or Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.19 OR (Or Word Data of Source Register to Data in Memory) Takes the logical OR of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 118 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: OR R2, @R3 Instruction bit pattern : 1001 0100 0010 0011 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 119: Orh (Or Half-Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.20 ORH (Or Half-word Data of Source Register to Data in Memory) Takes the logical OR of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 120 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORH R2, @R3 Instruction bit pattern : 1001 0101 0010 0011 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 121: Orb (Or Byte Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.21 ORB (Or Byte Data of Source Register to Data in Memory) Takes the logical OR of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 122 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORB R2, @R3 Instruction bit pattern : 1001 0110 0010 0011 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 123: Eor (Exclusive Or Word Data Of Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) Takes the logical exclusive OR of the word data in "Ri" and the word data in "Rj", stores the results to "Ri". ■ EOR (Exclusive Or Word Data of Source Register to Destination Register) Assembler format: EOR Rj, Ri Ri eor Rj →...
Page 124: Eor (Exclusive Or Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) Takes the logical exclusive OR of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 125 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EOR R2, @R3 Instruction bit pattern : 1001 1100 0010 0011 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 126: Eorh (Exclusive Or Half-Word Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) Takes the logical exclusive OR of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 127 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORH R2, @R3 Instruction bit pattern : 1001 1101 0010 0011 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 128: Eorb (Exclusive Or Byte Data Of Source Register To Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) Takes the logical exclusive OR of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 129 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORB R2, @R3 Instruction bit pattern : 1001 1110 0010 0011 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory...
Page 130: Bandl (And 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 131 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDL #0, @R3 Instruction bit pattern : 1000 0000 0000 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 132: Bandh (And 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 133 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDH #0, @R3 Instruction bit pattern : 1000 0001 0000 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 134: Borl (Or 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 135 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORL #1, @R3 Instruction bit pattern : 1001 0000 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 136: Borh (Or 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
Page 137 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORH #1, @R3 Instruction bit pattern : 1001 0001 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 138: Beorl (Eor 4-Bit Immediate Data To Lower 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri".
Page 139 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORL #1, @R3 Instruction bit pattern : 1001 1000 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 140: Beorh (Eor 4-Bit Immediate Data To Higher 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri".
Page 141 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORH #1, @R3 Instruction bit pattern : 1001 1001 0001 0011 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Memory Memory 12345678 12345678 12345679 12345679 N Z V C N Z V C 0 0 0 0 0 0 0 0...
Page 142: Btstl (Test Lower 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", places the results in the condition code register (CCR). ■...
Page 143: Btsth (Test Higher 4 Bits Of Byte Data In Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", places the results in the condition code register (CCR). ■...
Page 144: Mul (Multiply Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.34 MUL (Multiply Word Data) Multiplies the word data in "Rj" by the word data in "Ri" as signed numbers, and stores the resulting signed 64-bit data with the high word in the multiplication/division register (MDH), and the low word in the multiplication/division register (MDL).
Page 145 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MUL R2, R3 Instruction bit pattern : 1010 1111 0010 0011 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 8 0 0 0 0 0 0 1 x x x x x x x x...
Page 146: Mulu (Multiply Unsigned Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.35 MULU (Multiply Unsigned Word Data) Multiplies the word data in "Rj" by the word data in "Ri" as unsigned numbers, and stores the resulting unsigned 64-bit data with the high word in the multiplication/ division register (MDH), and the low word in the multiplication/division register (MDL).
Page 147 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULU R2, R3 Instruction bit pattern : 1010 1011 0010 0011 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 8 0 0 0 0 0 0 1 x x x x x x x x...
Page 148: Mulh (Multiply Half-Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.36 MULH (Multiply Half-word Data) Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as signed numbers, and stores the resulting signed 32-bit data in the multiplication/division register (MDL).
Page 149 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULH R2, R3 Instruction bit pattern : 1011 1111 0010 0011 F E D C B A 9 8 F E D C B A 9 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x x x x x x x...
Page 150: Muluh (Multiply Unsigned Half-Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.37 MULUH (Multiply Unsigned Half-word Data) Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as unsigned numbers, and stores the resulting unsigned 32-bit data in the multiplication/division register (MDL).
Page 151 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULUH R2, R3 Instruction bit pattern : 1011 1011 0010 0011 F E D C B A 9 8 F E D C B A 9 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x x x x x x x...
Page 152: Div0S (Initial Setting Up For Signed Division)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.38 DIV0S (Initial Setting Up for Signed Division) This command is used for signed division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL"...
Page 153 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV0S R2 Instruction bit pattern : 1001 0111 0100 0010 0 F F F F F F F 0 F F F F F F F 0 0 0 0 0 0 0 0 F F F F F F F F F F F F F F F 0 F F F F F F F 0...
Page 154: Div0U (Initial Setting Up For Unsigned Division)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.39 DIV0U (Initial Setting Up for Unsigned Division) This command is used for unsigned division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL" register and the remainder in the multiplication/division register (MDH). The "MDH"...
Page 155 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV0U R2 Instruction bit pattern : 1001 0111 0101 0010 0 0 F F F F F F 0 0 F F F F F F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F F F 0 0 F F F F F F 0...
Page 156: Div1 (Main Process Of Division)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) This instruction is used in unsigned division. It should be used in combinations such as DIV0U and DIV1 x 32. ■ DIV1 (Main Process of Division) Assembler format: DIV1 Ri Operation: {MDH, MDL} <...
Page 157 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV1 R2 Instruction bit pattern : 1001 0111 0110 0010 0 0 F F F F F F 0 0 F F F F F F 0 0 F F F F F F 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1...
Page 158: Div2 (Correction When Remainder Is 0)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.41 DIV2 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV2 (Correction when Remainder is 0) Assembler format: DIV2 Ri Operation:...
Page 159 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV2 R2 Instruction bit pattern : 1001 0111 0111 0010 0 0 F F F F F F 0 0 F F F F F F 0 0 F F F F F F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F...
Page 160: Div3 (Correction When Remainder Is 0)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.42 DIV3 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV3 (Correction when Remainder is 0) Assembler format: DIV3 Operation:...
Page 161: Div4S (Correction Answer For Signed Division)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.43 DIV4S (Correction Answer for Signed Division) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S. ■ DIV4S (Correction Answer for Signed Division) Assembler format: DIV4S Operation:...
Page 162: Lsl (Logical Shift To The Left Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.44 LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
Page 163: Lsl (Logical Shift To The Left Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.45 LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ LSL (Logical Shift to the Left Direction) Assembler format: LSL #u4, Ri Ri <<...
Page 164: Lsl2 (Logical Shift To The Left Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.46 LSL2 (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, stores the results to "Ri". ■ LSL2 (Logical Shift to the Left Direction) Assembler format: LSL2 #u4, Ri Ri <<...
Page 165: Lsr (Logical Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.47 LSR (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
Page 166: Lsr (Logical Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.48 LSR (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ LSR (Logical Shift to the Right Direction) Assembler format: LSR #u4, Ri Ri >>...
Page 167: Lsr2 (Logical Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.49 LSR2 (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result to "Ri". ■ LSR2 (Logical Shift to the Right Direction) Assembler format: LSR2 #u4, Ri Ri >>...
Page 168: Asr (Arithmetic Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.50 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
Page 169: Asr (Arithmetic Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.51 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ ASR (Arithmetic Shift to the Right Direction) Assembler format: ASR #u4, Ri Ri >>...
Page 170: Asr2 (Arithmetic Shift To The Right Direction)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.52 ASR2 (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result to "Ri". ■ ASR2 (Arithmetic Shift to the Right Direction) Assembler format: ASR2 #u4, Ri Ri >>...
Page 171: Ldi:32 (Load Immediate 32-Bit Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) Loads 1 word of immediate data to "Ri". ■ LDI:32 (Load Immediate 32-bit Data to Destination Register) Assembler format: LDI:32 #i32, Ri i32 → Ri Operation: Flag change: –...
Page 172: Ldi:20 (Load Immediate 20-Bit Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) Extends the 20-bit immediate data with 12 zeros in the higher bits, loads to "Ri". ■ LDI:20 (Load Immediate 20-bit Data to Destination Register) Assembler format: LDI:20 #i20, Ri extu (i20) →...
Page 173: Ldi:8 (Load Immediate 8-Bit Data To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) Extends the 8-bit immediate data with 24 zeros in the higher bits, loads to "Ri". ■ LDI:8 (Load Immediate 8-bit Data to Destination Register) Assembler format: LDI:8 #i8, Ri extu (i8) →...
Page 174: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.56 LD (Load Word Data in Memory to Register) Loads the word data at memory address "Rj" to "Ri". ■ LD (Load Word Data in Memory to Register) Assembler format: LD @Rj, Ri (Rj) → Ri Operation: Flag change: –...
Page 175: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.57 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R13 + Rj)" to "Ri". ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R13, Rj), Ri (R13 + Rj) →...
Page 176: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.58 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R14 + o8 × 4)" to "Ri". The value "o8" is a signed calculation. ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R14, disp10), Ri (R14 + o8 ×...
Page 177: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.59 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R15 + u4 × 4)" to "Ri". The value "u4" is an unsigned calculation. ■ LD (Load Word Data in Memory to Register) Assembler format: LD @ (R15, udisp6), Ri (R15 + u4 ×...
Page 178: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.60 LD (Load Word Data in Memory to Register) Loads the word data at memory address "R15" to "Rj", and adds 4 to the value of "R15". If "R15" is given as parameter "Ri", the value read from the memory will be loaded into memory address "R15".
Page 179: Ld (Load Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.61 LD (Load Word Data in Memory to Register) Loads the word data at memory address "R15" to dedicated register "Rs", and adds 4 to the value of "R15". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
Page 180 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, MDH Instruction bit pattern : 0000 0111 1000 0100 1 2 3 4 5 6 7 4 1 2 3 4 5 6 7 8 x x x x x x x x 8 7 6 5 4 3 2 1 12345670 12345670...
Page 181: Ld (Load Word Data In Memory To Program Status Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.62 LD (Load Word Data in Memory to Program Status Register) Loads the word data at memory address "R15" to the program status (PS), and adds 4 to the value of "R15". At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...
Page 182 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, PS Instruction bit pattern : 0000 0111 1001 0000 1 2 3 4 5 6 7 4 1 2 3 4 5 6 7 8 F F F F F 8 D 5 F F F 8 F 8 C 0 12345670 12345670...
Page 183: Lduh (Load Half-Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.63 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "Rj", loads to "Ri". ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @Rj, Ri extu (( Rj)) →...
Page 184: Lduh (Load Half-Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.64 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R13 + Rj)", loads to "Ri". ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @(R13, Rj), Ri extu (( R13 + Rj)) →...
Page 185: Lduh (Load Half-Word Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.65 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R14 + o8 × 2)", loads to "Ri". The value "o8" is a signed calculation. ■ LDUH (Load Half-word Data in Memory to Register) Assembler format: LDUH @(R14, disp9), Ri extu (( R14 + o8 ×...
Page 186: Ldub (Load Byte Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.66 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "Rj", loads to "Ri". ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @Rj, Ri extu ((Rj)) →...
Page 187: Ldub (Load Byte Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.67 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R13 + Rj)", loads to "Ri". ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @ (R13, Rj), Ri extu ((R13 + Rj)) →...
Page 188: Ldub (Load Byte Data In Memory To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.68 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R14 + o8)", loads to "Ri". The value "o8" is a signed calculation. ■ LDUB (Load Byte Data in Memory to Register) Assembler format: LDUB @ (R14, disp8), Ri extu ((R14 + o8)) →...
Page 189: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.69 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "Rj". ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @Rj Ri → (Rj) Operation: Flag change: –...
Page 190: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.70 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R13 + Rj)". ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @ (R13, Rj) Ri →...
Page 191: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.71 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R14 + o8 × 4)". The value "o8" is a signed calculation. ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri,@ (R14, disp10) Ri →...
Page 192: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.72 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R15 + u4 × 4)". The value "u4" is an unsigned calculation. ■ ST (Store Word Data in Register to Memory) Assembler format: ST Ri, @ (R15, udisp6) Ri →...
Page 193: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.73 ST (Store Word Data in Register to Memory) Subtracts 4 from the value of "R15", stores the word data in "Ri" to the memory address indicated by the new value of "R15". If "R15" is given as the parameter "Ri", the data transfer will use the value of "R15" before subtraction.
Page 194: St (Store Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.74 ST (Store Word Data in Register to Memory) Subtracts 4 from the value of "R15", stores the word data in dedicated register "Rs" to the memory address indicated by the new value of "R15". If a non-existent dedicated register is given as "Rs", undefined data will be transferred.
Page 195: St (Store Word Data In Program Status Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.75 ST (Store Word Data in Program Status Register to Memory) Subtracts 4 from the value of "R15", stores the word data in the program status (PS) to the memory address indicated by the new value of "R15". ■...
Page 196: Sth (Store Half-Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.76 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "Rj". ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @Rj Ri → (Rj) Operation: Flag change: –...
Page 197: Sth (Store Half-Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R13 + Rj)". ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @(R13, Rj) Ri →...
Page 198: Sth (Store Half-Word Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.78 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R14 + o8 × 2)". The value "o8" is a signed calculation. ■ STH (Store Half-word Data in Register to Memory) Assembler format: STH Ri, @(R14, disp9) Ri →...
Page 199: Stb (Store Byte Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.79 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "Rj". ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @Rj Ri → (Rj) Operation: Flag change: –...
Page 200: Stb (Store Byte Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.80 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R13 + Rj)". ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @ (R13, Rj) Ri →...
Page 201: Stb (Store Byte Data In Register To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.81 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R14 + o8)". The value "o8" is a signed calculation. ■ STB (Store Byte Data in Register to Memory) Assembler format: STB Ri, @ (R14, disp8) Ri →...
Page 202: Mov (Move Word Data In Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.82 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in "Rj" to "Ri". ■ MOV (Move Word Data in Source Register to Destination Register) Assembler format: MOV Rj, Ri Rj →...
Page 203: Mov (Move Word Data In Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.83 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in dedicated register "Rs" to general-purpose register "Ri". If the number of a non-existent dedicated register is given as "Rs", undefined data will be transferred.
Page 204: Mov (Move Word Data In Program Status Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.84 MOV (Move Word Data in Program Status Register to Destination Register) Moves the word data in the program status (PS) to general-purpose register "Ri". ■ MOV (Move Word Data in Program Status Register to Destination Register) Assembler format: MOV PS, Ri PS →...
Page 205: Mov (Move Word Data In Source Register To Destination Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.85 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in general-purpose register "Ri" to dedicated register "Rs". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
Page 206: Mov (Move Word Data In Source Register To Program Status Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.86 MOV (Move Word Data in Source Register to Program Status Register) Moves the word data in general-purpose register Ri to the program status (PS). At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...
Page 207 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MOV R3, PS Instruction bit pattern : 0000 0111 0001 0011 F F F 3 F 8 D 5 F F F 3 F 8 D 5 x x x x x x x x F F F 3 F 8 D 5 Before execution After execution...
Page 208: Jmp (Jump)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.87 JMP (Jump) This is a branching instruction with no delay slot. Branches to the address indicated by "Ri". ■ JMP (Jump) Assembler format: JMP @Ri Ri → PC Operation: Flag change: – – – –...
Page 209: Call (Call Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.88 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), branch to the address indicated by "lavel12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11"...
Page 210: Call (Call Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.89 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), a branch to the address indicated by "Ri" occurs. ■...
Page 211: Ret (Return From Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.90 RET (Return from Subroutine) This is a branching instruction with no delay slot. Branches to the address indicated by the return pointer (RP). ■ RET (Return from Subroutine) Assembler format: RP → PC Operation: Flag change: –...
Page 212: Int (Software Interrupt)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.91 INT (Software Interrupt) Stores the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. Writes "0" to the "S" flag in the condition code register (CCR), and uses the "SSP" as the stack pointer for the following steps.
Page 213 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INT #20H Instruction bit pattern : 0001 1111 0010 0000 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 7 F F F F F F 8 0 0 0 F F C 0 0 0 0 0 F F C 0 0...
Page 214: Inte (Software Interrupt For Emulator)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.92 INTE (Software Interrupt for Emulator) This software interrupt instruction is used for debugging. It stores the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition code register (CCR), and uses the "SSP"...
Page 215 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INTE Instruction bit pattern : 1001 1111 0011 0000 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 7 F F F F F F 8 4 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0...
Page 216: Reti (Return From Interrupt)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.93 RETI (Return from Interrupt) Loads data from the stack indicated by "R15" to the program counter (PC) and program status (PS), and retakes control from the interrupt handler. This instruction requires the S flag in the register (CCR) to be executed in a state of "0". Do not manipulate the S flag in the normal interrupt handler;...
Page 217 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: RETI Instruction bit pattern : 1001 0111 0011 0000 7 F F F F F F 8 4 0 0 0 0 0 0 0 7 F F F F F F 8 8 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 F F 0 0 9 0 B C...
Page 218: Bcc (Branch Relative If Condition Satisfied)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.94 Bcc (Branch Relative if Condition Satisfied) This branching instruction has no delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8"...
Page 219 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles: Branch: 2 cycles Not branch: 1 cycle Instruction format: rel8 Example: BHI label label: ; BHI instruction address + 50 Instruction bit pattern : 1110 1111 0010 1000 F F 8 0 0 0 0 0 F F 8 0 0 0 5 2 N Z V C N Z V C...
Page 220: Jmp:d (Jump)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.95 JMP:D (Jump) This branching instruction has a delay slot. Branches to the address indicated by "Ri". ■ JMP:D (Jump) Assembler format: JMP : D @Ri Ri → PC Operation: Flag change: – – – –...
Page 221: Call:d (Call Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.96 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", branch to the address indicated by "label12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11"...
Page 222 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: CALL:D label LDI : 8 #0, R2 ; Instruction placed in delay slot label: ; CALL: D instruction address + 122 Instruction bit pattern : 1101 1000 1001 0000 x x x x x x x x 0 0 0 0 0 0 0 0 F F 8 0 0 1 2 2 F F 8 0 0 0 0 0...
Page 223: Call:d (Call Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.97 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", it branches to the address indicated by "Ri". ■...
Page 224 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: CALL : D @R1 LDI : 8 #1, R1 ; Instruction placed in delay slot Instruction bit pattern : 1001 1111 0001 0001 F F F F F 8 0 0 0 0 0 0 0 0 0 1 F F F F F 8 0 0 8 0 0 0 F F F E x x x x...
Page 225: Ret:d (Return From Subroutine)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.98 RET:D (Return from Subroutine) This is a branching instruction with a delay slot. Branches to the address indicated by the "RP". ■ RET:D (Return from Subroutine) Assembler format: RET : D RP → PC Operation: Flag change: –...
Page 226 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: RET : D MOV R0, R1 ; Instruction placed in delay slot Instruction bit pattern : 1001 1111 0010 0000 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 x x x x x x x x 8 0 0 0 A E 8 6...
Page 227: Bcc:d (Branch Relative If Condition Satisfied)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.99 Bcc:D (Branch Relative if Condition Satisfied) This is a branching instruction with a delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8"...
Page 228 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles: 1 cycle Instruction format: rel8 Example: BHI:D label LDI :8 #255, R1 ; Instruction placed in delay slot label: ; BHI: D instruction address + 50 Instruction bit pattern : 1111 1111 0010 1000 8 9 4 7 9 7 A F 0 0 0 0 0 0 F F F F 8 0 0 0 0 0...
Page 229: Dmov (Move Word Data From Direct Address To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.100 DMOV (Move Word Data from Direct Address to Register) Transfers, to "R13", the word data at the direct address corresponding to 4 times the value of "dir8". ■ DMOV (Move Word Data from Direct Address to Register) Assembler format: DMOV @dir10, R13 (dir8 ×...
Page 230: Dmov (Move Word Data From Register To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.101 DMOV (Move Word Data from Register to Direct Address) Transfers the word data in "R13" to the direct address corresponding to 4 times the value of "dir8". ■ DMOV (Move Word Data from Register to Direct Address) Assembler format: DMOV R13, @dir10 R13 →...
Page 231: Dmov (Move Word Data From Direct Address To Post Increment Register Indirect Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) Transfers the word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R13". After the data transfer, it increments the value of "R13"...
Page 232 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @88H, @R13+ Instruction bit pattern : 0000 1100 0010 0010 F F F F 1 2 4 8 F F F F 1 2 4 C Memory Memory 00000088 1 4 1 4 2 1 3 5 00000088 1 4 1 4 2 1 3 5 1 4 1 4 2 1 3 5...
Page 233: Dmov (Move Word Data From Post Increment Register Indirect Address To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in "R13" to the direct address corresponding to 4 times the value "dir8". After the data transfer, it increments the value of "R13"...
Page 234 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R13+, @54H Instruction bit pattern : 0001 1100 0001 0101 F F F F 1 2 4 8 F F F F 1 2 4 C Memory Memory x x x x x x x x 00000054 00000054 8 9 4 7 9 1 A F...
Page 235: Dmov (Move Word Data From Direct Address To Pre-Decrement Register Indirect Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address) Decrements the value of "R15" by 4, then transfers word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R15". ■...
Page 236 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @2CH, @ – R15 Instruction bit pattern : 0000 1011 0000 1011 7 F F F F F 8 8 7 F F F F F 8 4 Memory Memory 0000002C 0000002C 8 2 A 2 8 2 A 9 8 2 A 2 8 2 A 9 x x x x x x x x...
Page 237: Dmov (Move Word Data From Post Increment Register Indirect Address To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in "R15" to the direct address corresponding to 4 times the value "dir8". After the data transfer, it increments the value of "R15"...
Page 238 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R15+, @38H Instruction bit pattern : 0001 1011 0000 1110 7 F F E E E 8 0 7 F F E E E 8 4 Memory Memory x x x x x x x x 00000038 00000038 8 3 4 3 8 3 4 A...
Page 239: Dmovh (Move Half-Word Data From Direct Address To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.106 DMOVH (Move Half-word Data from Direct Address to Register) Transfers the half-word data at the direct address corresponding to 2 times the value "dir8" to "R13". Uses zeros to extend the higher 16 bits of data. ■...
Page 240: Dmovh (Move Half-Word Data From Register To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.107 DMOVH (Move Half-word Data from Register to Direct Address) Transfers the half-word data from "R13" to the direct address corresponding to 2 times the value "dir8". ■ DMOVH (Move Half-word Data from Register to Direct Address) Assembler format: DMOVH R13, @dir9 R13 →...
Page 241: Dmovh (Move Half-Word Data From Direct Address To Post Increment Register Indirect Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address) Transfers the half-word data at the direct address corresponding to 2 times the value "dir8" to the address indicated by "R13". After the data transfer, it increments the value of "R13"...
Page 242 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @88H, @R13+ Instruction bit pattern : 0000 1101 0100 0100 F F 0 0 0 0 5 2 F F 0 0 0 0 5 4 Memory Memory 00000088 1 3 7 4 00000088 1 3 7 4 x x x x...
Page 243: Dmovh (Move Half-Word Data From Post Increment Register Indirect Address To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address) Transfers the half-word data at the address indicated by "R13" to the direct address corresponding to 2 times the value "dir8". After the data transfer, it increments the value of "R13"...
Page 244 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @R13+, @52H Instruction bit pattern : 0001 1101 0010 1001 F F 8 0 1 2 2 0 F F 8 0 1 2 2 2 Memory Memory x x x x 00000052 00000052 8 9 3 3 8 9 3 3...
Page 245: Dmovb (Move Byte Data From Direct Address To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) Transfers the byte data at the address indicated by the value "dir8" to "R13". Uses zeros to extend the higher 24 bits of data. ■ DMOVB (Move Byte Data from Direct Address to Register) Assembler format: DMOVB @dir8, R13 (dir8) →...
Page 246: Dmovb (Move Byte Data From Register To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.111 DMOVB (Move Byte Data from Register to Direct Address) Transfers the byte data from "R13" to the direct address indicated by the value "dir8". ■ DMOVB (Move Byte Data from Register to Direct Address) Assembler format: DMOVB R13, @dir8 R13 →...
Page 247: Dmovb (Move Byte Data From Direct Address To Post Increment Register Indirect Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) Moves the byte data at the direct address indicated by the value "dir8" to the address indicated by "R13". After the data transfer, it increments the value of "R13" by 1. ■...
Page 248 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @71H, @R13+ Instruction bit pattern : 0000 1110 0111 0001 8 8 0 0 1 2 3 4 8 8 0 0 1 2 3 5 Memory Memory 00000071 00000071 88001234 88001234 88001235 88001235 Before execution After execution...
Page 249: Dmovb (Move Byte Data From Post Increment Register Indirect Address To Direct Address)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) Transfers the byte data at the address indicated by "R13" to the direct address indicated by the value "dir8". After the data transfer, it increments the value of "R13" by 1. ■...
Page 250 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @R13+, @57H Instruction bit pattern : 0001 1110 0101 0111 F F 8 0 1 2 2 0 F F 8 0 1 2 2 1 Memory Memory 00000057 00000057 FF801220 FF801220 FF801221 FF801221 Before execution After execution...
Page 251: Ldres (Load Word Data In Memory To Resource)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.114 LDRES (Load Word Data in Memory to Resource) Transfers the word data at the address indicated by "Ri" to the resource on channel "u4". Increments the value of "Ri" by 4. ■ LDRES (Load Word Data in Memory to Resource) Assembler format: LDRES @Ri+, #u4 (Ri) →...
Page 252: Stres (Store Word Data In Resource To Memory)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.115 STRES (Store Word Data in Resource to Memory) Transfers the word data at the resource on channel "u4" to the address indicated by "Ri". Increments the value of "Ri" by 4. ■ STRES (Store Word Data in Resource to Memory) Assembler format: STRES #u4, @Ri+ Resource on channel u4 →...
Page 253: Copop (Coprocessor Operation)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.116 COPOP (Coprocessor Operation) Transfers the 16-bit data consisting of parameters "CC", "CRj", "CRi" to the coprocessor indicated by channel number "u4". Basically, this operation is a calculation between registers within the coprocessor. The calculation process indicated by the value "CC" is carried out between coprocessor registers "CRj"...
Page 254 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPOP #15, #1, CR3, CR4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.116-1 will have the following effect on coprocessor operation.
Page 255: Copld (Load 32-Bit Data From Register To Coprocessor Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) Transfers the 16-bit data consisting of parameters "CC", "Rj", "CRi" to the coprocessor indicated by channel number "u4", then on the next cycle transfers the contents of CPU general-purpose register "Rj"...
Page 256 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPLD #15, #4, R8, CR1 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the contents of general-purpose register "R8" are transferred through the bus to that coprocessor. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC"...
Page 257: Copst (Store 32-Bit Data From Coprocessor Register To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number "u4", then on the next cycle loads the data output by the coprocessor into CPU general-purpose register "Ri".
Page 258 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPST #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the output data of the coprocessor are transferred through the bus to that coprocessor. Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC"...
Page 259: Copsv (Save 32-Bit Data From Coprocessor Register To Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number u4, then on the next cycle loads the data output by the coprocessor to CPU general-purpose register "Ri".
Page 260 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPSV #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the data output by the coprocessor is loaded into the CPU through the data bus. Note that no "coprocessor error"...
Page 261: Nop (No Operation)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.120 NOP (No Operation) This instruction performs no operation. ■ NOP (No Operation) Assembler format: Operation: This instruction performs no operation. Flag change: – – – – N, Z, V, and C: Unchanged Execution cycles: 1 cycle Instruction format: Example:...
Page 262: Andccr (And Condition Code Register And Immediate Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.121 ANDCCR (And Condition Code Register and Immediate Data) Takes the logical AND of the byte data in the condition code register (CCR) and the immediate data, and returns the results into the "CCR". ■ ANDCCR (And Condition Code Register and Immediate Data) Assembler format: ANDCCR #u8 CCR and u8 →...
Page 263: Orccr (Or Condition Code Register And Immediate Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.122 ORCCR (Or Condition Code Register and Immediate Data) Takes the logical OR of the byte data in the condition code register (CCR) and the immediate data, and returns the results into the "CCR". ■ ORCCR (Or Condition Code Register and Immediate Data) Assembler format: ORCCR #u8 CCR or u8 →...
Page 264: Stilm (Set Immediate Data To Interrupt Level Mask Register)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) Transfers the immediate data to the interrupt level mask register (ILM) in the program status (PS). Only the lower 5 bits (bit4 to bit0) of the immediate data are valid. At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM"...
Page 265: Addsp (Add Stack Pointer And Immediate Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.124 ADDSP (Add Stack Pointer and Immediate Data) Adds 4 times the immediate data as a signed extended value, to the value in "R15". ■ ADDSP (Add Stack Pointer and Immediate Data) Assembler format: ADDSP #s10 R15 + exts (s8 ×...
Page 266: Extsb (Sign Extend From Byte Data To Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.125 EXTSB (Sign Extend from Byte Data to Word Data) Extends the byte data indicated by "Ri" to word data as a signed binary value. ■ EXTSB (Sign Extend from Byte Data to Word Data) Assembler format: EXTSB Ri exts (Ri) →...
Page 267: Extub (Unsign Extend From Byte Data To Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) Extends the byte data indicated by "Ri" to word data as an unsigned binary value. ■ EXTUB (Unsign Extend from Byte Data to Word Data) Assembler format: EXTUB Ri extu (Ri) →...
Page 268: Extsh (Sign Extend From Byte Data To Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.127 EXTSH (Sign Extend from Byte Data to Word Data) Extends the half-word data indicated by "Ri" to word data as a signed binary value. ■ EXTSH (Sign Extend from Byte Data to Word Data) Assembler format: EXTSH Ri exts (Ri) →...
Page 269: Extuh (Unsigned Extend From Byte Data To Word Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) Extends the half-word data indicated by "Ri" to word data as an unsigned binary value. ■ EXTUH (Unsigned Extend from Byte Data to Word Data) Assembler format: EXTUH Ri extu (Ri) →...
Page 270: Ldm0 (Load Multiple Registers)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.129 LDM0 (Load Multiple Registers) The "LDM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist". (See Table 7.129-1.) Registers are processed in ascending numerical order. ■ LDM0 (Load Multiple Registers) Assembler format: LDM0 (reglist) Operation:...
Page 271 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LDM0 (R3, R4) Instruction bit pattern : 1000 1100 0001 1000 x x x x x x x x 9 0 B C 9 3 6 3 x x x x x x x x 8 3 4 3 8 3 4 A 7 F F F F F C 0 7 F F F F F C 8...
Page 272: Ldm1 (Load Multiple Registers)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.130 LDM1 (Load Multiple Registers) The LDM1 instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.130-1.). Registers are processed in ascending numerical order. If "R15" is specified in the parameter "reglist", the final contents of "R15" will be read from memory.
Page 273 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Table 7.130-1 Bit Values and Register Numbers for "reglist" (LDM1) Register Register Example: LDM1 (R10, R11, R12) Instruction bit pattern : 1000 1101 0001 1100 x x x x x x x x 8 F E 3 9 E 8 A x x x x x x x x 9 0 B C 9 3 6 3 x x x x x x x x...
Page 274: Stm0 (Store Multiple Registers)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.131 STM0 (Store Multiple Registers) The "STM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist" (See Table 7.131-1.) . Registers are processed in descending numerical order. ■ STM0 (Store Multiple Registers) Assembler format: STM0 (reglist) Operation:...
Page 275 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM0 (R2, R3) Instruction bit pattern : 1000 1110 0011 0000 9 0 B C 9 3 6 3 9 0 B C 9 3 6 3 8 3 4 3 8 3 4 A 8 3 4 3 8 3 4 A 7 F F F F F C 8 7 F F F F F C 0...
Page 276: Stm1 (Store Multiple Registers)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.132 STM1 (Store Multiple Registers) The "STM1" instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.132-1.). Registers are processed in descending numerical order. If "R15" is specified in the parameter "reglist", the contents of "R15" retained before the instruction is executed will be written to memory.
Page 277 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM1 (R10, R11, R12) Instruction bit pattern : 1000 1111 0011 1000 8 F E 3 9 E 8 A 8 F E 3 9 E 8 A 9 0 B C 9 3 6 3 9 0 B C 9 3 6 3 8 D F 7 8 8 E 4 8 D F 7 8 8 E 4...
Page 278: Enter (Enter Function)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.133 ENTER (Enter Function) This instruction is used for stack frame generation processing for high level languages. The value "u8" is calculated as an unsigned value. ■ ENTER (Enter Function) Assembler format: ENTER #u10 R14 → (R15 – 4) Operation: R15 –...
Page 279 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ENTER #0CH Instruction bit pattern : 0000 1111 0000 0011 7 F F F F F F 4 8 0 0 0 0 0 0 0 7 F F F F F F 8 7 F F F F F E C Memory Memory...
Page 280: Leave (Leave Function)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.134 LEAVE (Leave Function) This instruction is used for stack frame release processing for high level languages. ■ LEAVE (Leave Function) Assembler format: LEAVE R14 + 4 → R15 Operation: (R15 – 4) → R14 Flag change: –...
Page 281 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LEAVE Instruction bit pattern : 1001 1111 1001 0000 8 0 0 0 0 0 0 0 7 F F F F F F 4 7 F F F F F E C 7 F F F F F F 8 Memory Memory x x x x...
Page 282: Xchb (Exchange Byte Data)
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.135 XCHB (Exchange Byte Data) Exchanges the contents of the byte address indicated by "Rj" and those indicated by "Ri". The lower 8 bits of data originally at "Ri" are transferred to the byte address indicated by "Rj", and the data originally at "Rj"...
Page 283 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: XCHB @R1, R0 Instruction bit pattern : 1000 1010 0001 0000 0 0 0 0 0 0 7 8 0 0 0 0 0 0 F D 8 0 0 0 0 0 0 2 8 0 0 0 0 0 0 2 Memory Memory...
Page 284 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS...
Page 285: Appendix
APPENDIX The appendix section includes lists of CPU instructions used in the FR family, as well as instruction map diagrams. APPENDIX A Instruction Lists APPENDIX B Instruction Maps...
Page 286: Appendix A Instruction Lists
APPENDIX A Instruction Lists APPENDIX A Instruction Lists Appendix A includes a description of symbols used in instruction lists, plus the instruction lists. A.1 Symbols Used in Instruction Lists A.2 Instruction Lists...
Page 287: Symbols Used In Instruction Lists
APPENDIX A Instruction Lists Symbols Used in Instruction Lists This section describes symbols used in the FR family instruction lists. ■ Symbols Used in Instruction Lists ● Symbols in Mnemonic and Operation Columns • i4 ..... 4-bit immediate data, range 0 to 15 with zero extension, and –16 to –1 with minus extension •...
Page 288 APPENDIX A Instruction Lists ● Format Column A to F ..format TYPE-A through F as described in Section "6.1 Instruction Formats". ● OP Column "OP" codes have the following significance according to the format type listed in the format column. •...
Page 289: Instruction Lists
APPENDIX A Instruction Lists Instruction Lists The full instruction set of the FR family CPU is 165 instructions, consisting of the following sixteen types. These instructions are listed in Table A.2-1 through Table A.2-16. • Add/Subtract Instructions (10 Instructions) • Compare Instructions (3 Instructions) •...
Page 290 APPENDIX A Instruction Lists Table A.2-2 Compare Instructions (3 Instructions) FLAG Mnemonic Format Operation Remarks NZVC CMP Rj, Ri CCCC Ri – Rj CMP #i4, Ri CCCC Ri – extu(i4) Zero extension CMP2 #i4, Ri CCCC Ri – extn(i4) Minus extension Table A.2-3 Logical Calculation Instructions (12 Instructions) FLAG Mnemonic...
Page 291 APPENDIX A Instruction Lists Table A.2-5 Multiply/Divide Instructions (10 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Rj × Ri → MDH,MDL Rj,Ri CCC – 32bits × 32bits=64bits Rj × Ri → MDH,MDL MULU Rj,Ri CCC – Unsigned Rj × Ri → MDL MULH Rj,Ri CC –...
Page 292 APPENDIX A Instruction Lists Table A.2-8 Memory Load Instructions (13 Instructions) FLAG Mnemonic Format Operation Remarks NZVC (Rj) → Ri LD @Rj, Ri – – – – (R13+Rj) → Ri LD @(R13,Rj), Ri – – – – (R14+disp10) → Ri LD @(R14,disp10), Ri –...
Page 293 APPENDIX A Instruction Lists Table A.2-9 Memory Store Instructions (13 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → (Rj) ST Ri, @Rj – – – – Word Ri → (R13+Rj) ST Ri, @(R13,Rj) – – – – Word Ri → (R14+disp10) ST Ri, @(R14,disp10) –...
Page 294 APPENDIX A Instruction Lists Table A.2-11 Non-delayed Branching Instructions (23 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → PC JMP @Ri 97-0 – – – – PC+2 → RP ,PC+2+rel11×2 → PC CALL label12 – – – – PC+2 → RP, Ri → PC CALL @Ri 97-1 –...
Page 295 APPENDIX A Instruction Lists Table A.2-12 Delayed Branching Instructions (20 Instructions) FLAG Mnemonic Format Operation Remarks NZVC Ri → PC JMP:D @Ri 9F-0 – – – – PC+4 → RP ,PC+2+rel11×2 → PC CALL:D label12 – – – – PC+4 → RP, Ri → PC CALL:D @Ri 9F-1 –...
Page 296 APPENDIX A Instruction Lists Table A.2-13 Direct Addressing Instructions (14 Instructions) FLAG Mnemonic Format Operation Remarks NZVC (dir10) → R13 DMOV @dir10, R13 – – – – Word R13 → (dir10) DMOV R13, @dir10 – – – – Word (dir10) → (R13),R13+=4 DMOV @dir10, @R13+ –...
Page 297 APPENDIX A Instruction Lists Table A.2-16 Other Instructions (16 Instructions) FLAG Mnemonic Format Operation Remarks NZVC 9F-A – – – – No change CCR and u8 → CCR ANDCCR #u8 CCCC CCR or u8 → CCR ORCCR #u8 CCCC – – – – u8 → ILM STILM #u8 Sets "ILM"...
Page 298: Appendix B Instruction Maps
APPENDIX B Instruction Maps APPENDIX B Instruction Maps This appendix presents FR family instruction map and "E" format. B.1 Instruction Map B.2 "E" Format...
Page 299: Instruction Map
APPENDIX B Instruction Maps Instruction Map This section shows instruction maps for FR family CPU. ■ Instruction Map Table B.1-1 Instruction Map Lower 4 bits...
Page 300: E" Format
APPENDIX B Instruction Maps "E" Format This section shows "E" format for FR family CPU. ■ "E" Format Table B.2-1 "E" Format Higher 8 bits LD @R15+,Ri ST Ri,@–R15 JMP @Ri JMP:D @Ri MOV Ri,PS MOV PS,Ri CALL @Ri CALL:D @Ri −...
Page 301: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetical order.
Page 302 INDEX Index And Word Data AND (And Word Data of Source Register to Data in Memory) ..........86 ADD (Add 4-bit Immediate Data to Destination AND (And Word Data of Source Register to Register)..........73 Destination Register)......85 ADD (Add Word Data of Source Register to ANDB Destination Register) ......
Page 303 INDEX Bit Patterns COPLD Relation between Bit Patterns "Ri" and "Rj" and COPLD (Load 32-bit Data from Register to Register Values........64 Coprocessor Register) ......231 BORH COPOP BORH (Or 4-bit Immediate Data to Higher 4 Bits of COPOP (Coprocessor Operation) .......229 Byte Data in Memory) ......
Page 304 INDEX Examples of Programing Delayed Branching DMOV (Move Word Data from Direct Address to Instructions ........... 62 Register) ..........205 Overview of Branching with Delayed Branching DMOV (Move Word Data from Register to Direct Instructions ........... 58 Address) ..........206 Restrictions on Interrupts during Processing of DMOVB (Move Byte Data from Direct Address to Delayed Branching Instructions ....
Page 305 INDEX DMOVB (Move Byte Data from Register to Direct How to Use Undefined Instruction Exceptions..43 Address)..........222 Operations of Undefined Instruction Exceptions ..43 Overview of Exception Processing .......42 DMOVH Overview of Undefined Instruction Exceptions..43 DMOVH (Move Half-word Data from Direct Address Time to Start of Undefined Instruction Exception to Post Increment Register Indirect Address) Processing..........43...
Page 306 INDEX Interlocking Produced by Reference to "R15" and "PC" Values Saved for "INTE" Instruction Execution ............46 General-purpose Registers after Changing the "S" Flag .......... 57 "PC" Values Saved for Undefined Instruction Overview of General-purpose Registers....15 Exceptions ........... 43 Special Uses of General-purpose Registers ...
Page 307 INDEX Precautionary Information for Use of "INT" Instructions........... 45 Time to Start of Trap Processing for "INT" JMP (Jump) .............184 Instructions........... 45 JMP:D (Jump) ..........196 INTE Jump "INTE" Instruction Operation......46 JMP (Jump) .............184 "PC" Values Saved for "INTE" Instruction Execution ............
Page 308 INDEX LDI:8 (Load Immediate 8-bit Data to Destination DMOVH (Move Half-word Data from Direct Address Register)..........149 to Register)......... 215 DMOVH (Move Half-word Data from Post Increment Load Multiple Registers Register Indirect Address to Direct Address) LDM0 (Load Multiple Registers)....... 246 ............
Page 309 INDEX ORCCR ORCCR (Or Condition Code Register and Immediate Data) ..........239 Relation of Step Trace Traps to "NMI" and External Interrupts..........47 ORH (Or Half-word Data of Source Register to Data No Operation in Memory) ...........95 NOP (No Operation) ........237 Non-delayed Branching Instructions Examples of Processing Non-delayed Branching Instructions...........
Page 310 INDEX Interrupt Level Mask Register (ILM: Bit 20 to bit 16) ............19 Sample LD (Load Word Data in Memory to Program Status Sample Configuration of an FR Family Device ..3 Register)..........157 Sample Configuration of the FR Family CPU ..4 Note on PS Register..........
Page 311 INDEX STILM EORB (Exclusive Or Byte Data of Source Register to Data in Memory)......... 104 STILM (Set Immediate Data to Interrupt Level Mask Register) ..........240 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ....102 MOV (Move Word Data in Source Register to STM0 (Store Multiple Registers) .......250 Destination Register) ...
Page 312 INDEX System Stack Pointer How to Use Undefined Instruction Exceptions..43 Functions of the System Stack Pointer and User Stack Operations of Undefined Instruction Exceptions Pointer ..........28 ............43 System Stack Pointer (SSP),User Stack Pointer (USP) Overview of Undefined Instruction Exceptions ..43 ............
Page 313 CM71-00101-5E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL December 2007 the fifth edition FUJITSU LIMITED Electronic Devices Published Edited Strategic Business Development Dept...

This manual is also suitable for:

Fr series

Fujitsu FR Family Instruction Manual

Chapter 1 Fr Family Overview

Chapter 2 Memory Architecture

Chapter 3 Register Descriptions

Chapter 4 Reset and "Eit" Processing

Chapter 5 Precautionary Information for the Fr Family Cpu

Chapter 6 Instruction Overview

Chapter 7 Detailed Execution Instructions

Appendix

APPENDIX A Instruction Lists

APPENDIX B Instruction Maps

Index

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Summary of Contents for Fujitsu FR Family