External Interrupt Request Register (Eirr) - Fujitsu FR60 Hardware Manual

9.2.2

External Interrupt Request Register (EIRR)

This section describes the bit configuration and functions of the external interrupt
Request Register EIRR.
■ External Interrupt Request Register (EIRR: External Interrupt Request Register)
Figure 9.2-3 shows the bit configuration of the external interrupt Request Register (EIRR).
Figure 9.2-3 Bit Configuration of the External Interrupt Request Register (EIRR)
Address: 000040
The EIRR register, when it is read, indicates that a corresponding external interrupt request
exists. When it is written to, the contents of the flip-flop (NMI flag) that indicates this request are
cleared. If "1" is read from the EIRR register, an external interrupt request exists at the pin
corresponding to this bit.
Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" to this register has no effect.
For a read by a read-modify-write instruction, "1" is read.
Note:
The NMI flag cannot be read or written to by a user.
For information about the NMI flag, see "NMI" in Section "9.3 Operation of the External Interrupt
and NMI Controller".
When the INT0 to INT7 pins input the "H" level in the stop state, their respective ER0 to ER7 bits
are set to "1".
CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
bit 15 14 13
ER7 ER6 ER5
H
R/W R/W R/W
12 11 10 9
ER4 ER3 ER2 ER1
R/W R/W R/W R/W
8 Initial value
00000000
ER0
B
R/W
319