Fujitsu FR60 Hardware Manual page 191

If "0" is set, the read strobe signal (RD for memory -> I/O and IORD for I/O -> memory) and the
write strobe signal (IOWR for memory -> I/O and WR0 to WR3 and WR for I/O -> memory) on
the transfer source access side are output at the same timing.
If "1" is set, the read strobe signal is output one cycle longer than the write strobe signal to
secure a hold time for data at the transfer source access side when sending it to the transfer
destination.
[bit29, bit28, bit21, bit20] WR01/WR00, WR11/WR10 (I/O Idle Wait) :
These bits set the number of idle cycles for continuous access during DMA fly-by access.
Table 4.2-33 lists the settings for the number of I/O idle cycles.
Table 4.2-33 Settings for the Number of I/O Idle Cycles
WRn1
0
0
1
1
If one or more cycles is set as the number of idle cycles, cycles equal to the number specified
are inserted after I/O access during DMA fly-by access. During the idle cycles, all CSn and
strobe output is negated and the data pin is set to the high impedance state.
[bit27 to bit24, bit19 to bit16, bit11 to bit8] IW03 to IW00,IW13 to IW10 (I/O Access Wait) :
These bits set the number of auto-wait cycles for I/O access during DMA fly-by access.
Table 4.2-34 lists the settings for the number of I/O wait cycles.
Table 4.2-34 Settings for the Number of I/O Wait Cycles
IWn3 IWn2
0 0
0 0
1 1
Because data is synchronized between the transfer source and transfer destination, the I/O side
setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory),
whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more
wait cycles than specified by the IWnn bits may be inserted.
WRn0 Setting of the number of I/O idle cycles
0
1
0
1
Setting the number of I/O Access Wait Cycles
IWn1 IWn0
0 0
0 1
...
1 1
CHAPTER 4 EXTERNAL BUS INTERFACE
Setting the number of I/O Idle Cycles
0 cycle
1 cycle
2 cycles
3 cycles
Number of I/O wait cycles
0 cycle
1 cycle
...
15 cycles
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