Csn -> Rd/Wrn Setup And Rd/Wrn -> Csn Hold Setting - Fujitsu FR60 Hardware Manual

4.5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting
This section shows the operation timing for the CSn -> RD/WRn setup and RD/WRn ->
CSn hold settings.
■ Operation Timing for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings
Figure 4.5-9 shows the operation timing for (TYP3 to TYP0=0000
Figure 4.5-9 Timing Chart for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings
READ
WRITE
• Setting "1" for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to
be set. Set this bit to extend the period between chip select assertion and read/write strobe.
• Setting "1" for the W00 bit of the AWR register enables the RD/WRn -> CSn hold delay to be
set. Set this bit to extend the period between read/write strobe negation and chip select
negation.
• The CSn -> RD/WRn setup delay (W01 bit) and RD/WRn -> CSn hold delay (W00 bit) can
be set independently.
• When making successive accesses within the same chip select area without negating the
chip select, neither a CSn -> RD/WRn setup delay nor an RD/WRn -> CSn hold delay is
inserted.
• If a setup cycle for determining the address or a hold cycle for determining the address is
needed, set "1" for the address -> CSn delay setting (W02 bit of the AWR register).
MCLK
A31 to A00
AS
CSn
CS->RD/WR
RD
D31 to D00
WRn
D31 to D00
CHAPTER 4 EXTERNAL BUS INTERFACE
RD/WR->CS
Delay Delay
AWR=000B ).
B H
213