Fujitsu FR60 Hardware Manual page 18

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■ Clock Generation Control is changed.
(The followings sentences are added. The following section describes the generation and control of each
clock. For detailed information about the registers and flags described below, see "3.12.5 Block Diagram
of Clock Generation Controller" and "3.12.6 Register of Clock Generation Controller".
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The symbol "φ", which is shown in Table 3.12-4, Table 3.12-9, Table 3.12-13, Table 3.12-16, Table 3.12-
20, Table 3.12-21 and Table 3.12-22, indicates the basic clock that is achieved by dividing the source clock
by two or performing PLL oscillation. Therefore, the system base clock is the clock which is generated
where the above base clock is generated.)
Figure 3.12-1 Block Diagram of Clock Generation Controller is changed.
109
( [Watchdog controller] is changed.)
112 Note is added.
Table 3.12-9 Oscillation Stabilization Wait Settings is changed.
(CS1 → OS1)
114
(CS0 → OS0)
116 [bit9] SYNCR (SYNChronous Reset enable) is changed.
■ Time Base Counter Clear Register (CTBR) is changed.
(The followings sentences are added. The bits are automatically cleared when the CPU is not in operation
in such cases as stop/sleep mode and DMA transfer. Therefore, if the above conditions occur, the watchdog
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reset is delayed automatically. However, it will not be delayed, if a request to hold an external bus (BRQ)
has been accepted. For this reason, select the sleep mode before entering a hold request (BRQ), when
intending to hold the external bus for a long period.)
■ Watchdog Reset Postpone Register (WPR) is deleted.
(119)
[Postponing a watchdog reset] is changed.
(Once the watchdog timer is started, the program must write {A5
125
dog reset postpone register (WPR). → Once the watchdog timer is started, the program must write "A5
and "5A " in this order to the time base counter clear register (CTBR).)
H
136 [Sleep mode transition] is added.
❍ Synchronous standby operations is changed.
137
(❍ Normal and synchronous standby operations → ❍ Synchronous standby operations)
■ Stop Mode is changed.
138
([Stop mode transition] is added.)
Table 3.14-1 Mode Settings is changed.
141
(The description in * is deleted.)
Table 3.14-2 Function of internal ROM enable is changed.
(The description in *1 is deleted.)
142
Table 3.14-3 Settings of the Initial Bus Width is changed.
(Only for MB91302A and MB91V301A is deleted.)
■ Functions of Bits in the Area Select Registers (ASR0 to ASR7) is changed.
(The area select registers (ASR0 to ASR7) specify the start address of each chip select area (CS0 to CS7).
151
is added.)
(ASR0 to 7 registers. → ACR0 to ACR7 registers.)
Figure 4.2-2 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) is changed.
153
(Note is added.)
❍ Example of setting ASRs and ASZ3 to ASZ0 is changed.
(10000000
181
H
(00200000
H
Changes (For details, refer to main body.)
→ 0FFFFFFF
)
H
→ 001FFFFF
)
H
} and {5A
H
xiv
} in this order to the watch-
H
"
H