Configuration Of The Control Registers - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.3.2

Configuration of the Control Registers

Control registers include the cache size register (ISIZE) and the instruction cache
register (ICHCR).
This section describes the functions of these registers.
■ Configuration of Cache Size Register (ISIZE)
Figure 3.3-3 shows the configuration of the cache size register (ISIZE) bits.
Figure 3.3-3 Configuration of the Control Register (ISIZE) Bits
bit
00000307
H
The following describes the functions of the cache size register (ISIZE) bits.
[bit1, bit0] SIZE1, SIZE0
These bits set the capacity of the instruction cache. Depending on the setting, the cache
size, IRAM capacity, and address map used in RAM mode vary as shown in Figure 3.3-5. If
you have changed the cache capacity, be sure to flash the cache and unlock the entries
before turning on the cache.
Table 3.3-1 Cache Size Registers
SIZE1
■ Instruction Cache Control Register (ICHCR)
The instruction cache control register (ICHCR: I-CacHe Control Register) controls instruction
cache operation.
Writing to the ICHCR does not affect the cache operation of an instruction fetched during the
subsequent three cycles.
Figure 3.3-4 shows the configuration of the instruction cache control register.
Figure 3.3-4 Configuration of Instruction Cache Control Register (ICHCR) Bits
bit
000003E7
H
54
7 6 5
- - -
- - -
SIZE0
0 0
0 1
1 0
1 1
7 6 5
RAM - GBLK ALFL
R/W - R/W
4 3 2 1
- - - SIZE1 SIZE0
- - - R/W
1 Kbyte
2 Kbytes
4 Kbytes (Initial value)
Setting prohibited
4 3 2 1
EOLK ELKR FLSH
R/W R/W R/W R/W
0 Initial value
------10
B
R/W
Capacity
0 Initial value
0-000000
ENAB
B
R/W