Reset Sequence - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.11.3 Reset Sequence

When a reset source no longer exists, the device starts to execute the reset sequence.
A reset sequence has different operations depending on the reset level.
This section describes the operations of the reset sequence for different reset levels.
■ Setting Initialization Reset (INIT) Clear Sequence
If a settings initialization reset (INIT) request is cleared, the following operations are performed
one step at a time for the device.
1) Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state.
2) For the oscillation stabilization wait time (set with bit3 and bit2 [OS1 and OS0 bits] in the
STCR), maintain the operation initialization reset (RST) state and stop the internal clock.
3) In the operation initialization reset (RST) state, start internal clock operation.
4) Clear the operation initialization reset (RST) and enter the normal operating state.
5) Read the mode vector from address 000FFFF8
6) Write the mode vector to the MODR (mode register) at address 000007FD
7) Read the reset vector from address 000FFFFC
8) Write the reset vector to the program counter (PC).
9) The program starts execution from the address loaded in the program counter (PC).
■ Operation Initialization Reset (RST) Clear Sequence
If an operation initialization reset (RST) request is cleared, the following operations are
performed one step at a time for the device.
1) Clear the operation initialization reset (RST) and enter the normal operating state.
2) Read the mode vector from address 000FFFF8
3) Write the mode vector to the MODR (mode register) at address 000007FD
4) Read the reset vector from address 000FFFFC
5) Write the reset vector to the program counter (PC).
6) The program starts execution from the address loaded in the program counter (PC).
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