Fujitsu FR60 Hardware Manual page 66

CHAPTER 3 CPU AND CONTROL UNITS
■ Internal Architecture
The FR family CPU uses the Harvard architecture, which has separate buses for instructions
and data. A 32-bit/16-bit bus converter is connected to the 32-bit bus (F-bus), providing an
interface between the CPU and peripheral resources. A Harvard/Princeton bus converter is
connected to both the I-bus and D-bus, providing an interface between the CUP and bus
controllers.
Figure 3.2-1 shows connections in the internal architecture.
Data RAM
32-bit
16-bit
Bus converter
16
R-bus
Peripheral resources
46
Figure 3.2-1 Internal Architecture
FR60 CPU
D-bus
I address
D address
D data
Address
Data
Internal I/O
I-bus
32
32
I data
32
32
Bus converter
32
32
F-bus
Bus controller
External address
24
Harvard
External data
Princeton
32