Fujitsu FR60 Hardware Manual page 286

32-bit microcontroller mb91301 series
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CHAPTER 5 I/O PORT
Table 5.2-1 Functions of the Port Function Registers (PFR) (3 / 5)
Register name
Bit name
(DDRB)
PFRB1
00061B
H
(DDRB)
266
Bit value
0,0,0
General-purpose port (PB0, PB1, PB2)
DACK0, DEOP0 output (FR30-compatible for fly-by
0,0,1
transfer)
DACK0, DEOP0 output (FR30-compatible for two-
0,1,0
cycle transfer RD timing)
DACK0, DEOP0 output (FR30-compatible for two-
0,1,1
AK02,
cycle transfer WRn timing)
AK01,
DACK0, DEOP0 output (FR30-compatible for two-
AK00
1,0,0
cycle transfer WE timing)
DACK0, DEOP0 output (FR30-compatible for two-
1,0,1
cycle transfer WRn/RD timing)
DACK0, DEOP0 output (FR30-compatible for two-
1,1,0
cycle transfer WE, RD timing)
1,1,1
DACK0, DEOP0 output (chip select timing)
0,0
General-purpose port input (PB2)
DES0,
0,1
General-purpose port output (PB2)
PB2
1,0
DMAC: DSTP0 input (setting prohibited)
1,1
DMAC: DEOP0 output
0,0,0
General-purpose port (PB3, PB4, PB5)
DACK1, DEOP1 output (FR30-compatible for fly-by
0,0,1
transfer)
DACK1, DEOP1 output (FR30-compatible for two-
0,1,0
cycle transfer RD timing)
DACK1, DEOP1 output (FR30-compatible for two-
0,1,1
AK12,
cycle transfer WRn timing)
AK11,
DACK1, DEOP1 output (FR30-compatible for two-
AK10
1,0,0
cycle transfer WE timing)
DACK1, DEOP1 output (FR30-compatible for two-
1,0,1
cycle transfer WRn/RD timing)
DACK1, DEOP1 output (FR30-compatible for two-
1,1,0
cycle transfer WE, RD timing)
1,1,1
DACK1, DEOP1 output (chip select timing)
0,0
General-purpose port input (PB5)
DES1,
0,1
General-purpose port output (PB5)
PB5
1,0
DMAC: DSTP1 input (setting prohibited)
1,1
DMAC: DEOP1 output
Function
Initial
value
000
00
000
00

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