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Fujitsu MB91460 SERIES FR60 User Manual

32-bit microcontroller
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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
- PRELIMINARY -
32-BIT MICROCONTROLLER
MB91460 Series
User's Manual
CM71-xxxxx-1E
FR60
Version 1.00
2006-10-22

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  Summary of Contents for Fujitsu MB91460 SERIES FR60

  • Page 1 FUJITSU SEMICONDUCTOR CONTROLLER MANUAL - PRELIMINARY - CM71-xxxxx-1E 32-BIT MICROCONTROLLER MB91460 Series User’s Manual Version 1.00 2006-10-22 FR60...
  • Page 2 FUJITSU LIMITED...
  • Page 3 FR60 32-BIT MICROCONTROLLER MB91460 Series User’s Manual...
  • Page 4 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
  • Page 5: Table Of Contents

    Chapter 1 Introduction ... 1 How to Handle the Device ... 1 Instruction for Users... 3 Caution: debug-related matters ... 6 How to Use This Document ... 7 Chapter 2 MB91460 Rev.A/Rev.B Overview ... 11 Overview... 11 Features... 11 MB91460 Series Product Lineup ... 19 Block Diagram ...
  • Page 6 EIT Vector Table... 122 Multiple EIT Processing ... 123 Operation ... 125 Caution ... 128 Chapter 7 Branch Instruction ... 129 Branch Instruction with Delay Slot ... 129 Operation of Branch Instruction with Delay Slot ... 129 Actual Example (with Delay Slot)... 130 Restrictions on Branch Instruction with Delay Slot ...
  • Page 7 Explanations of Registers ... 169 Chapter 12 Instruction Cache... 179 General description... 179 Main body structure ... 179 Operating mode conditions... 185 Cacheable areas in the instruction cache... 186 Settings for handling the I-Cache ... 186 Chapter 13 Clock Control ... 189 Overview...
  • Page 8 Configuration ... 250 Registers... 251 Operation ... 253 Settings... 259 Q&A ... 260 Caution ... 262 Chapter 19 Timebase Timer... 263 Overview... 263 Features... 263 Configuration ... 264 Register ... 265 Operation ... 267 Setting... 268 Q & A ... 269 Caution ...
  • Page 9 Register ... 301 Operation ... 303 Setting... 306 Q & A ... 307 Caution ... 309 Chapter 24 Interrupt Control ... 311 Overview... 311 Features... 311 Configuration ... 312 Registers... 313 Operation ... 318 Setting... 319 Q & A ... 319 Caution ...
  • Page 10 Register ... 389 Operation ... 391 Setting... 393 Q & A ... 394 Caution ... 395 Chapter 29 MPU / EDSU ... 397 Overview... 397 Features... 398 Break Functions... 399 Registers... 407 Quick Reference ... 429 Chapter 30 I/O Ports ... 431 I/O Ports Functions ...
  • Page 11 Chapter 34 CAN Controller ... 691 Overview... 691 Register Description ... 692 Functional Description ... 720 CAN Application... 724 Chapter 35 Free-Run Timer ... 733 Overview... 733 Features... 733 Configuration Diagram... 734 Registers... 735 Operation ... 739 Setting... 741 Q & A ... 742 Caution ...
  • Page 12 Features... 795 Configuration ... 797 Registers... 799 Operation ... 808 Setting... 811 Q & A ... 813 Caution ... 821 Chapter 40 Pulse Frequency Modulator... 823 PFM Overview ... 823 Reload Counter Registers ... 826 Reload Counter Operation... 830 PFM Operation and Setting ... 833 Chapter 41 Up/Down Counter...
  • Page 13 Registers... 911 Operation ... 913 Setting... 914 Q & A ... 915 Caution ... 916 Chapter 46 Alarm Comparator ... 917 Overview... 917 Block Diagram ... 917 Alarm Comparator Control/Status Register (ACSR)... 918 Operation Modes ... 919 Chapter 47 LCD Controller ... 921 Overview...
  • Page 14 Application Note... 973 Chapter 51 Low Voltage Reset/Interrupt ... 975 Overview... 975 Features... 975 Registers... 976 Chapter 52 Regulator Control ... 979 Overview... 979 Features... 979 Registers... 980 Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM ... 983 Overview... 983 Check for Boot Conditions ... 983 Registers modified by Boot ROM ...
  • Page 17: Chapter 1 Introduction

    Chapter 1 Introduction 1. How to Handle the Device ■ Device Handling Instructions This chapter describes latch-up prevention and pin termination. ● To set latch-up prevention Latch up may occur on CMOS ICs when the applied voltage for input terminals or output terminals is higher than V or lower than V , or a voltage higher than the maximum rating voltage is applied between V not to apply a voltage higher than the maximum rating voltage since latch up may surge electric current and result in...
  • Page 18 Chapter 1 Introduction 1.How to Handle the Device ● Caution: during the PLL clock operation Even if oscillator is disconnected or input is stopped while selecting PLL clock, self-excited oscillation circuit in the PLL may continue running at self-running frequency. This self-running operation is not covered by guarantee. ●...
  • Page 19: Instruction For Users

    2. Instruction for Users ■ Clock Controls By inputting “L” to INIT, ensure clock oscillation stabilization time. ■ Switching of dual-purpose port Use PFR (Port function register) to switch between PORT and dual-purpose port. ■ Low-power-consumption mode • For standby mode, enable synchronous standby (TBCR.SYNCS=“1”) and then use the following sequences. (LDI #value_of_standby, R0 (LDI...
  • Page 20 Chapter 1 Introduction 2.Instruction for Users ■ Caution: PS register Because some commands previously proceed PS register, interrupt processing routine may be broken during the use of debugger or displayed data on PS flag may be updated due to the following excecptional operations ((1) and (2)).
  • Page 21 ■ Caution: writing to registers which include a status flag Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function, note that you should not clear status flag unintentionally. That is, take care not to clear the flag for status bit and make control bit to be the expected value during the writing.
  • Page 22: Caution: Debug-Related Matters

    Chapter 1 Introduction 3.Caution: debug-related matters 3. Caution: debug-related matters ■ Stepwise execution of RETI command Under the circumstances where interruption is often generated when carrying out stepwise execution, only relevant interrupt processing routine is repeatedly executed after the stepwise execution of RETI. Therefore, main routine or low-level interruption program will not be executed.
  • Page 23: How To Use This Document

    4. How to Use This Document ■ Main terminology: This table shows main terminology used for FR60. Term 32-bit-wide bus for internal instruction. I-bus Since FR60 series employ internal Harvard architecture, instruction and data are independent bus. For I-bus, Harverd/Prinston-bus-converter is connected. Internal 32-bit-wide data bus.
  • Page 24 Chapter 1 Introduction 4.How to Use This Document ■ Access size and address position Offset Address There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note that some registers have restricted access. For more information, see “3.2. I/O Map (Page No.24)” or “Detail Description of Register”...
  • Page 25 ■ About access size and bit position Register name Register mark (1) Counter control register (Higher byte) This is the register (higher byte) which controls up/down counter operation. CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word) CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word) M16E/Reserved bit15: Enable 16-bit mode M16E (CCRH0 only)
  • Page 26 Chapter 1 Introduction 4.How to Use This Document ■ Meaning of Bit Attribute Symbols : Readable : Writable : Reading operation during read/modify/write operation. “/” (Slash) R/W: Readable and writable. (The read value is the value written.) “,” (comma) R,W: Values are different between read and write. (The read value is different from the value written.) : The read value is “0”.
  • Page 27: Chapter 2 Mb91460 Rev.a/Rev.b Overview

    Chapter 2 MB91460 Rev.A/Rev.B Overview 1. Overview MB91460 is a series of standard microcontrollers containing a range of I/O peripherals and bus control functions. MB91460 features a 32-bit RISC CPU (FR60 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. MB91460 derivatives also contain up to 16 kByte instruction cache memory and other internal memories to improve the execution speed of the CPU.
  • Page 28 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • 4 words (16 bytes) per set • Variable capacity (4/2/1 kB) • Lock function enabling programs to be resident • Available as instruction RAM requiring no wait state when not used as an instruction cache •...
  • Page 29 • 3 types of transfer sources (external pins/internal peripherals/and software) • Up to 128 selectable internal transfer sources • Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed) • Transfer mode (Demand transfer/burst transfer/step transfer/block transfer) • Fly-by transfer supported (between external I/O and memory) •...
  • Page 30 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features 2.10 Peripheral Function • General-purpose port : Up to 288 • N channel open drain port out of above: 8 (for I • A/D converter : 32 channels (1 unit) • Series-parallel type • Resolution: 10 bits •...
  • Page 31 • 16-bit reload counter • Includes clock prescaler (f • Free-run timer : 16 bits x 8 channels • 16-bit free running counter, signals an interrupt when overflow or match with compare register • Includes prescaler (f • Timer data register has R/W access •...
  • Page 32 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • LIN-USART (LIN=Local Interconnect Network) : 16 channels • Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each) • With parity/without parity selectable • 1 or 2 stop bits selectable •...
  • Page 33 the range of 1 to 1.5 cycles of the resource clock (CLKP) • PFM (pulse frequency modulator) : 16 bits x 1 channel • 16-bit reload timers for generating high/low pulse waveforms • Includes clock prescaler (f • Sound Generator : 1 channel •...
  • Page 34 Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • Prescaler value for 32 kHz is 001FFF • Clock monitor (clock output function): 1 channel • Clock supervisor • Monitors external 32kHz and 4MHz for fails (e.g. crystal breaks) • Switches in case of fail to an available recovery clock (subclock or RC clock) •...
  • Page 35: Mb91460 Series Product Lineup

    3. MB91460 Series Product Lineup Feature Core frequency Resource frequency Technology Watchdog Watchdog (RC osc. based) Bit Search Reset Input (INITX) Clock Modulator Low Power Mode MAC (uDSP) MMU/MPU Flash Flash Protection D-bus RAM I/D-bus RAM I-bus RAM / I-Cache Boot-ROM / BI-ROM Free Running Timer Reload Timer...
  • Page 36 Chapter 2 MB91460 Rev.A/Rev.B Overview 3.MB91460 Series Product Lineup Feature ADC (10 bit) Alarm Comparator Supply Supervisor Clock Supervisor Main clock oscillator Sub clock oscillator RC Oscillator DSU4 EDSU JTAG Boundary Scan Supply Voltage Regulator Power Consumption Temperatur Range (Ta) Package Power on to PLL run Flash Download Time...
  • Page 37: Block Diagram

    Chapter 2 MB91460 Rev.A/Rev.B Overview 4.Block Diagram 4. Block Diagram The following illustration shows the block diagram of MB91460 series. Figure 4-1 Block Diagram MB91460 Series M−Bus D−Bus I−Bus F−Bus...
  • Page 38 Chapter 2 MB91460 Rev.A/Rev.B Overview 4.Block Diagram...
  • Page 39: Chapter 3 Mb91460 Series Basic Information

    Chapter 3 MB91460 Series Basic Information 1.Memory Map Chapter 3 MB91460 Series Basic Information This chapter describes MB91460 series basic information including Memory- and I/O map, inter- rupt vector table, pin function list, circuit type and pin state table for each device mode. 1.
  • Page 40: I/O Map

    Chapter 3 MB91460 Series Basic Information 2.I/O Map 2. I/O Map This section shows the association between memory space and each register of peripheral resources. • Table convention Address offset/Register name Address 000000 PDRD[R/W] xxxxxxxx Register initial value ("0", "1", "X" : undefined, "-" : not implemented) Register name (First column register is 4n address, Second column register is 4n+2 address...) Leftmost register address...
  • Page 41 Table 2-1 I/O Map Address PDR00 [R/W] 000000 XXXXXXXX PDR04 [R/W] 000004 XXXXXXXX PDR08 [R/W] 000008 XXXXXXXX PDR12 [R/W] 00000C XXXXXXXX PDR16 [R/W] 000010 XXXXXXXX PDR20 [R/W] 000014 XXXXXXXX PDR24 [R/W] 000018 XXXXXXXX PDR28 [R/W] 00001C XXXXXXXX PDR32 [R/W] 000020 XXXXXXXX 000024 00002C...
  • Page 42 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address SCR01 [R/W,W] 000048 00000000 ESCR01 [R/W] 00004C 00000X00 SCR02 [R/W,W] 000050 00000000 ESCR02 [R/W] 000054 00000X00 SCR03 [R/W,W] 000058 00000000 ESCR03 [R/W] 00005C 00000X00 SCR04 [R/W,W] 000060 00000000 ESCR04 [R/W] 000064 00000X00 SCR05 [R/W,W] 000068...
  • Page 43 Address BGR100 [R/W] 000080 00000000 BGR102 [R/W] 000084 00000000 BGR104 [R/W] 000088 00000000 BGR106 [R/W] 00008C 00000000 PWC20 [R/W] 000090 - - - - - - XX XXXXXXXX 000094 res. PWC21 [R/W] 000098 - - - - - - XX XXXXXXXX 00009C res.
  • Page 44 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IBCR0 [R/W] 0000D0 00000000 ITMKH0 [R/W] 0000D4 00 - - - - 11 0000D8 res. IBCR1 [R/W] 0000DC 00000000 ITMKH1 [R/W] 0000E0 00 - - - - 11 0000E4 res. 0000E8 LCDCMR [R/W] - - - - 0000 0000EC...
  • Page 45 Address PTMR02 [R] 000120 11111111 11111111 PDUT02 [W] 000124 XXXXXXXX XXXXXXXX PTMR03 [R] 000128 11111111 11111111 PDUT03 [W] 00012C XXXXXXXX XXXXXXXX PTMR04 [R] 000130 11111111 11111111 PDUT04 [W] 000134 XXXXXXXX XXXXXXXX PTMR05 [R] 000138 11111111 11111111 PDUT05 [W] 00013C XXXXXXXX XXXXXXXX PTMR06 [R] 000140...
  • Page 46 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address P0TMCSRH 000170 [R/W] - 0 - 000 - 0 P0TMRLR [W] 000174 XXXXXXXX XXXXXXXX P1TMRLR [W] 000178 XXXXXXXX XXXXXXXX 00017C 000180 res. IPCP0 [R] 000184 XXXXXXXX XXXXXXXX IPCP2 [R] 000188 XXXXXXXX XXXXXXXX OCS01 [R/W] 00018C - - - 0 - - 00 0000 - - 00...
  • Page 47 Address TMRLR1 [W] 0001B8 XXXXXXXX XXXXXXXX 0001BC reserved TMRLR2 [W] 0001C0 XXXXXXXX XXXXXXXX 0001C4 reserved TMRLR3 [W] 0001C8 XXXXXXXX XXXXXXXX 0001CC reserved TMRLR4 [W] 0001D0 XXXXXXXX XXXXXXXX 0001D4 reserved TMRLR5 [W] 0001D8 XXXXXXXX XXXXXXXX 0001DC reserved TMRLR6 [W] 0001E0 XXXXXXXX XXXXXXXX 0001E4 reserved TMRLR7 [W]...
  • Page 48 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TCDT2 [R/W] 0001F8 XXXXXXXX XXXXXXXX TCDT3 [R/W] 0001FC XXXXXXXX XXXXXXXX 000200 000204 000208 00020C 000210 000214 000218 00021C 000220 000224 000228 00023C 000240 DMACR [R/W] 0 - - 00000 000244 00024C 000250 000254 Register...
  • Page 49 Address 000258 00027C SCR08 [R/W,W] 000280 00000000 ESCR08 [R/W] 000284 00000X00 SCR09 [R/W,W] 000288 00000000 ESCR09 [R/W] 00028C 00000X00 SCR10 [R/W,W] 000290 00000000 ESCR10 [R/W] 000294 00000X00 SCR11 [R/W,W] 000298 00000000 ESCR11 [R/W] 00029C 00000X00 SCR12 [R/W,W] 0002A0 00000000 ESCR12 [R/W] 0002A4 00000X00 SCR13 [R/W,W]...
  • Page 50 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address SCR14 [R/W,W] 0002B0 00000000 ESCR14 [R/W] 0002B4 00000X00 SCR15 [R/W,W] 0002B8 00000000 ESCR15 [R/W] 0002BC 00000X00 BGR108 [R/W] 0002C0 00000000 BGR110 [R/W] 0002C4 00000000 BGR112 [R/W] 0002C8 00000000 BGR114 [R/W] 0002CC 00000000 0002D0 res.
  • Page 51 Address TCDT5 [R/W] 0002F4 XXXXXXXX XXXXXXXX TCDT6 [R/W] 0002F8 XXXXXXXX XXXXXXXX TCDT7 [R/W] 0002FC XXXXXXXX XXXXXXXX UDRC1 [W] 000300 00000000 UDCCH0 [R/W] 000304 00001000 UDCCH1 [R/W] 000308 00001000 00030C UDRC3 [W] 000310 00000000 UDCCH2 [R/W] 000314 00001000 UDCCH3 [R/W] 000318 00001000 00031C GCN13 [R/W]...
  • Page 52 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address PTMR14 [R] 000340 11111111 PDUT14 [W] 000344 XXXXXXXX PTMR15 [R] 000348 11111111 PDUT15 [W] 00034C XXXXXXXX 000350 00035C 000360 res. DADR0 [R/W] 000364 - - - - - - XX XXXXXXXX IBCR2 [R/W] 000368 00000000...
  • Page 53 Address 0003D8 0003E0 0003E4 0003E8 0003EC 0003F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400 00043C Chapter 3 MB91460 Series Basic Information Register reserved reserved reserved BSD0 BSD1 [R/W] BSDC BSRR...
  • Page 54 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address ICR00 [R/W] 000440 ---11111 ICR04 [R/W] 000444 ---11111 ICR08 [R/W] 000448 ---11111 ICR12 [R/W] 00044C ---11111 ICR16 [R/W] 000450 ---11111 ICR20 [R/W] 000454 ---11111 ICR24 [R/W] 000458 ---11111 ICR28 [R/W] 00045C ---11111 ICR32 [R/W] 000460...
  • Page 55 Address PLLDIVM [R/W] 00048C - - - - 0000 PLLCTRL [R/W] 000490 - - - - 0000 OSCC1 [R/W] 000494 - - - - - 010 PORTEN [R/W] 000498 - - - - - - 00 0004A0 res. 0004A4 - - - - - - - - - - - XXXXX XXXXXXXX XXXXXXXX WTHR [R/W] 0004A8 - - - 00000...
  • Page 56 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address C340R [R/W] 0004D0 - - - - - - - 0 SHDE [R/W] 0004D4 0 - - - - - - - EXTLV [R/W] 0004D8 00000000 00000000 0004DC 00063C Register EISSRH [R/W] res.
  • Page 57 Address ASR0 [R/W] 000640 00000000 00000000 ASR1 [R/W] 000644 XXXXXXXX XXXXXXXX ASR2 [R/W] 000648 XXXXXXXX XXXXXXXX ASR3 [R/W] 00064C XXXXXXXX XXXXXXXX ASR4 [R/W] 000650 XXXXXXXX XXXXXXXX ASR5 [R/W] 000654 XXXXXXXX XXXXXXXX ASR6 [R/W] 000658 XXXXXXXX XXXXXXXX ASR7 [R/W] 00065C XXXXXXXX XXXXXXXX AWR0 [R/W] 000660 01111111 11111*11...
  • Page 58 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 0007FC res. 000800 000BFC TVCTW [W] 000C00 XXXXXXXX 000C04 000CFC PDRD00 [R] 000D00 XXXXXXXX PDRD04 [R] 000D04 XXXXXXXX PDRD08 [R] 000D08 XXXXXXXX PDRD12 [R] 000D0C XXXXXXXX PDRD16 [R] 000D10 XXXXXXXX PDRD20 [R] 000D14 XXXXXXXX PDRD24 [R]...
  • Page 59 Address DDR00 [R/W] 000D40 00000000 DDR04 [R/W] 000D44 00000000 DDR08 [R/W] 000D48 00000000 DDR12 [R/W] 000D4C 00000000 DDR16 [R/W] 000D50 00000000 DDR20 [R/W] 000D54 00000000 DDR24 [R/W] 000D58 00000000 DDR28 [R/W] 000D5C 00000000 DDR32 [R/W] 000D60 00000000 000D64 000D7C PFR00 [R/W] 000D80 11111111 PFR04 [R/W]...
  • Page 60 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000DA4 000DBC EPFR00 [R/W] 000DC0 00000000 EPFR04 [R/W] 000DC4 00000000 EPFR08 [R/W] 000DC8 00000000 EPFR12 [R/W] 000DCC 00000000 EPFR16 [R/W] 000DD0 00000000 EPFR20 [R/W] 000DD4 00000000 EPFR24 [R/W] 000DD8 00000000 EPFR28 [R/W] 000DDC 00000000 EPFR32 [R/W]...
  • Page 61 Address PODR00 [R/W] 000E00 00000000 PODR04 [R/W] 000E04 00000000 PODR08 [R/W] 000E08 00000000 PODR12 [R/W] 000E0C 00000000 PODR16 [R/W] 000E10 00000000 PODR20 [R/W] 000E14 00000000 PODR24 [R/W] 000E18 00000000 PODR28 [R/W] 000E1C 00000000 PODR32 [R/W] 000E20 00000000 000E24 000E3C PILR00 [R/W] 000E40 00000000 PILR04 [R/W]...
  • Page 62 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000E64 000E7C EPILR00 [R/W] 000E80 00000000 EPILR04 [R/W] 000E84 00000000 EPILR08 [R/W] 000E88 00000000 EPILR12 [R/W] 000E8C 00000000 EPILR16 [R/W] 000E90 00000000 EPILR20 [R/W] 000E94 00000000 EPILR24 [R/W] 000E98 00000000 EPILR28 [R/W] 000E9C 00000000 EPILR32 [R/W]...
  • Page 63 Address PPER00 [R/W] 000EC0 00000000 PPER04 [R/W] 000EC4 00000000 PPER08 [R/W] 000EC8 00000000 PPER12 [R/W] 000ECC 00000000 PPER16 [R/W] 000ED0 00000000 PPER20 [R/W] 000ED4 00000000 PPER24 [R/W] 000ED8 00000000 PPER28 [R/W] 000EDC 00000000 PPER32 [R/W] 000EE0 00000000 000EE4 000EFC PPCR00 [R/W] 000F00 11111111 PPCR04 [R/W]...
  • Page 64 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 000F24 000F3C 001000 001004 001008 00100C 001010 001014 001018 00101C 001020 001024 001028 006FFC FMCS [R/W] 007000 01101000 FMWT [R/W] 007004 11111111 11111111 007008 00700C 007010 007014 007FFC Register reserved DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
  • Page 65 Address 008000 MB91V460 Boot-ROM size is 4kB : 00B000 (instruction access is 1 waitcycle, data access is 1 waitcycle) 00BFFC CTRLR0 [R/W] 00C000 00000000 00000001 ERRCNT0 [R] 00C004 00000000 00000000 INTR0 [R] 00C008 00000000 00000000 BRPER0 [R/W] 00C00C 00000000 00000000 IF1CREQ0 [R/W] 00C010 00000000 00000001...
  • Page 66 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ0 [R/W] 00C040 00000000 00000001 IF2MSK20 [R/W] 00C044 11111111 11111111 IF2ARB20 [R/W] 00C048 00000000 00000000 IF2MCTR0 [R/W] 00C04C 00000000 00000000 IF2DTA10 [R/W] 00C050 00000000 00000000 IF2DTB10 [R/W] 00C054 00000000 00000000 00C058 00C05C IF2DTA20 [R/W] 00C060...
  • Page 67 Address TREQR20 [R] 00C080 00000000 00000000 TREQR40 [R] 00C084 00000000 00000000 TREQR60 [R] 00C088 00000000 00000000 TREQR80 [R] 00C08C 00000000 00000000 NEWDT20 [R] 00C090 00000000 00000000 NEWDT40 [R] 00C094 00000000 00000000 NEWDT60 [R] 00C098 00000000 00000000 NEWDT80 [R] 00C09C 00000000 00000000 INTPND20 [R] 00C0A0 00000000 00000000...
  • Page 68 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR1 [R/W] 00C100 00000000 00000001 ERRCNT1 [R] 00C104 00000000 00000000 INTR1 [R] 00C108 00000000 00000000 BRPER1 [R/W] 00C10C 00000000 00000000 IF1CREQ1 [R/W] 00C110 00000000 00000001 IF1MSK21 [R/W] 00C114 11111111 11111111 IF1ARB21 [R/W] 00C118 00000000 00000000 IF1MCTR1 [R/W]...
  • Page 69 Address IF2CREQ1 [R/W] 00C140 00000000 00000001 IF2MSK21 [R/W] 00C144 11111111 11111111 IF2ARB21 [R/W] 00C148 00000000 00000000 IF2MCTR1 [R/W] 00C14C 00000000 00000000 IF2DTA11 [R/W] 00C150 00000000 00000000 IF2DTB11 [R/W] 00C154 00000000 00000000 00C158 00C15C IF2DTA21 [R/W] 00C160 00000000 00000000 IF2DTB21 [R/W] 00C164 00000000 00000000 00C168...
  • Page 70 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR21 [R] 00C180 00000000 00000000 TREQR41 [R] 00C184 00000000 00000000 TREQR61 [R] 00C188 00000000 00000000 TREQR81 [R] 00C18C 00000000 00000000 NEWDT21 [R] 00C190 00000000 00000000 NEWDT41 [R] 00C194 00000000 00000000 NEWDT61 [R] 00C198 00000000 00000000 NEWDT81 [R]...
  • Page 71 Address CTRLR2 [R/W] 00C200 00000000 00000001 ERRCNT2 [R] 00C204 00000000 00000000 INTR2 [R] 00C208 00000000 00000000 BRPER2 [R/W] 00C20C 00000000 00000000 IF1CREQ2 [R/W] 00C210 00000000 00000001 IF1MSK22 [R/W] 00C214 11111111 11111111 IF1ARB22 [R/W] 00C218 00000000 00000000 IF1MCTR2 [R/W] 00C21C 00000000 00000000 IF1DTA12 [R/W] 00C220 00000000 00000000...
  • Page 72 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ2 [R/W] 00C240 00000000 00000001 IF2MSK22 [R/W] 00C244 11111111 11111111 IF2ARB22 [R/W] 00C248 00000000 00000000 IF2MCTR2 [R/W] 00C24C 00000000 00000000 IF2DTA12 [R/W] 00C250 00000000 00000000 IF2DTB12 [R/W] 00C254 00000000 00000000 00C258 00C25C IF2DTA22 [R/W] 00C260...
  • Page 73 Address TREQR22 [R] 00C280 00000000 00000000 TREQR42 [R] 00C284 00000000 00000000 TREQR62 [R] 00C288 00000000 00000000 TREQR82 [R] 00C28C 00000000 00000000 NEWDT22 [R] 00C290 00000000 00000000 NEWDT42 [R] 00C294 00000000 00000000 NEWDT62 [R] 00C298 00000000 00000000 NEWDT82 [R] 00C29C 00000000 00000000 INTPND22 [R] 00C2A0 00000000 00000000...
  • Page 74 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR3 [R/W] 00C300 00000000 00000001 ERRCNT3 [R] 00C304 00000000 00000000 INTR3 [R] 00C308 00000000 00000000 BRPER3 [R/W] 00C30C 00000000 00000000 IF1CREQ3 [R/W] 00C310 00000000 00000001 IF1MSK23 [R/W] 00C314 11111111 11111111 IF1ARB23 [R/W] 00C318 00000000 00000000 IF1MCTR3 [R/W]...
  • Page 75 Address IF2CREQ3 [R/W] 00C340 00000000 00000001 IF2MSK23 [R/W] 00C344 11111111 11111111 IF2ARB23 [R/W] 00C348 00000000 00000000 IF2MCTR3 [R/W] 00C34C 00000000 00000000 IF2DTA13 [R/W] 00C350 00000000 00000000 IF2DTB13 [R/W] 00C354 00000000 00000000 00C358 00C35C IF2DTA23 [R/W] 00C360 00000000 00000000 IF2DTB23 [R/W] 00C364 00000000 00000000 00C368...
  • Page 76 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR23 [R] 00C380 00000000 00000000 TREQR43 [R] 00C384 00000000 00000000 TREQR63 [R] 00C388 00000000 00000000 TREQR83 [R] 00C38C 00000000 00000000 NEWDT23 [R] 00C390 00000000 00000000 NEWDT43 [R] 00C394 00000000 00000000 NEWDT63 [R] 00C398 00000000 00000000 NEWDT83 [R]...
  • Page 77 Address CTRLR4 [R/W] 00C400 00000000 00000001 ERRCNT4 [R] 00C404 00000000 00000000 INTR4 [R] 00C408 00000000 00000000 BRPER4 [R/W] 00C40C 00000000 00000000 IF1CREQ4 [R/W] 00C410 00000000 00000001 IF1MSK24 [R/W] 00C414 11111111 11111111 IF1ARB24 [R/W] 00C418 00000000 00000000 IF1MCTR4 [R/W] 00C41C 00000000 00000000 IF1DTA14 [R/W] 00C420 00000000 00000000...
  • Page 78 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address IF2CREQ4 [R/W] 00C440 00000000 00000001 IF2MSK24 [R/W] 00C444 11111111 11111111 IF2ARB24 [R/W] 00C448 00000000 00000000 IF2MCTR4 [R/W] 00C44C 00000000 00000000 IF2DTA14 [R/W] 00C450 00000000 00000000 IF2DTB14 [R/W] 00C454 00000000 00000000 00C458 00C45C IF2DTA24 [R/W] 00C460...
  • Page 79 Address TREQR24 [R] 00C480 00000000 00000000 TREQR44 [R] 00C484 00000000 00000000 TREQR64 [R] 00C488 00000000 00000000 TREQR84 [R] 00C48C 00000000 00000000 NEWDT24 [R] 00C490 00000000 00000000 NEWDT44 [R] 00C494 00000000 00000000 NEWDT64 [R] 00C498 00000000 00000000 NEWDT84 [R] 00C49C 00000000 00000000 INTPND24 [R] 00C4A0 00000000 00000000...
  • Page 80 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address CTRLR5 [R/W] 00C500 00000000 00000001 ERRCNT5 [R] 00C504 00000000 00000000 INTR5 [R] 00C508 00000000 00000000 BRPER5 [R/W] 00C50C 00000000 00000000 IF1CREQ5 [R/W] 00C510 00000000 00000001 IF1MSK25 [R/W] 00C514 11111111 11111111 IF1ARB25 [R/W] 00C518 00000000 00000000 IF1MCTR5 [R/W]...
  • Page 81 Address IF2CREQ5 [R/W] 00C540 00000000 00000001 IF2MSK25 [R/W] 00C544 11111111 11111111 IF2ARB25 [R/W] 00C548 00000000 00000000 IF2MCTR5 [R/W] 00C54C 00000000 00000000 IF2DTA15 [R/W] 00C550 00000000 00000000 IF2DTB15 [R/W] 00C554 00000000 00000000 00C558 00C55C IF2DTA25 [R/W] 00C560 00000000 00000000 IF2DTB25 [R/W] 00C564 00000000 00000000 00C568...
  • Page 82 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address TREQR25 [R] 00C580 00000000 00000000 TREQR45 [R] 00C584 00000000 00000000 TREQR65 [R] 00C588 00000000 00000000 TREQR85 [R] 00C58C 00000000 00000000 NEWDT25 [R] 00C590 00000000 00000000 NEWDT45 [R] 00C594 00000000 00000000 NEWDT65 [R] 00C598 00000000 00000000 NEWDT85 [R]...
  • Page 83 Address 00F000 - - - - - - - - - - - - - - - - 11111100 00000000 00F004 - - - - - - - - - - - - - 000 00000000 10 - - 000000 00F008 00000000 00000000 00000000 00000000 00F00C...
  • Page 84 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 00F080 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX...
  • Page 85 Address 00F0C0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0CC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0D8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0DC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0E4...
  • Page 86 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 010000 013FFC 014000 017FFC 018000 01BFFC 01C000 01FFFC Register Cache TAG way 1 (010000 - 0107FC Cache TAG way 2 (014000 - 0147FC Cache RAM way 1 (018000 - 0187FC Cache RAM way 2 (01C000 - 01C7FC Block...
  • Page 87 Address 020000 MB91V460 D-RAM size is 64kB : 020000 02FFFC 030000 MB91V460 I-/D-RAM size is 64kB : 030000 (instruction access is 0 waitcycles, data access is 1 waitcycle) 03FFFC 040000 05FFFC 060000 07FFFC 080000 09FFFC 0A0000 0BFFFC 0C0000 0DFFFC 0E0000 0FFFF4 0FFFF8 0FFFFC...
  • Page 88 Chapter 3 MB91460 Series Basic Information 2.I/O Map Address 200000 27FFFC 280000 2FFFFC 300000 37FFFC 380000 3FFFFC 400000 47FFFC 480000 4FFFFC Write operations to address 0FFFF8 shown above will be read. Notes: Use a read access (byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt accep- tance of the CPU) to a preceding write access to the resources on R-bus (e.g.
  • Page 89: Interrupt Vector Table

    3. Interrupt Vector Table This section shows the allocation of interrupt and interrupt vector/interrupt register. Interrupt number Interrupt Decimal Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) Memory Protection excep- tion Co-processor fault trap Co-processor error trap INTE instruction...
  • Page 90 Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5...
  • Page 91 USART (LIN) 2 RX USART (LIN) 2 TX USART (LIN) 3 RX USART (LIN) 3 TX System reserved Delayed Interrupt System reserved System reserved USART (LIN, FIFO) 4 RX USART (LIN, FIFO) 4 TX USART (LIN, FIFO) 5 RX USART (LIN, FIFO) 5 TX USART (LIN, FIFO) 6 RX USART (LIN, FIFO) 6 TX USART (LIN, FIFO) 7 RX...
  • Page 92 Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5...
  • Page 93 Prog. Pulse Gen. 14 Prog. Pulse Gen. 15 Up/Down Counter 0 Up/Down Counter 1 Up/Down Counter 2 Up/Down Counter 3 Real Time Clock Calibration Unit A/D Converter 0 Alarm Comparator 0 Alarm Comparator 1 Low Voltage Detection Timebase Overflow PLL Clock Gear DMA Controller Main/Sub OSC stability wait Boot Security vector...
  • Page 94: Package

    Chapter 3 MB91460 Series Basic Information 4.Package 4. Package ■ BGA-660P-M02 package (BGA660-03EK): MB91V460 BGA660-03EK Figure 4-1 External Dimension of...
  • Page 95: Pin Assignment Diagram

    Chapter 3 MB91460 Series Basic Information 5.Pin Assignment Diagram 5. Pin Assignment Diagram ■ MB91V460 (BGA660 package) Figure 5-1 Pin Assignment Diagram of BGA660-03EK...
  • Page 96: Pin Definitions

    Chapter 3 MB91460 Series Basic Information 6.Pin Definitions 6. Pin Definitions AL38 P00_7 AJ37 P00_6 AJ36 P00_5 AJ35 P00_4 AH36 P00_3 AH35 P00_2 AK38 P00_1 AJ38 P00_0 AH37 P01_7 AG37 P01_6 AG35 P01_5 AG36 P01_4 AF35 P01_3 AF36 P01_2 AH38 P01_1 AF37 P01_0...
  • Page 97 P04_4 P04_3 P04_2 P04_1 P04_0 P05_7 P05_6 P05_5 P05_4 P05_3 P05_2 P05_1 P05_0 P06_7 P06_6 P06_5 P06_4 P06_3 P06_2 P06_1 P06_0 P07_7 P07_6 P07_5 P07_4 P07_3 P07_2 P07_1 P07_0 P08_7 P08_6 P08_5 BGRNTX BGRNTX P08_4 P08_3 P08_2 P08_1 P08_0 P09_7 P09_6 P09_5 P09_4...
  • Page 98 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P12_7 P12_6 P12_5 P12_4 P12_3 P12_2 P12_1 P12_0 P13_7 P13_6 P13_5 P13_4 P13_3 P13_2 P13_1 P13_0 P14_7 P14_6 P14_5...
  • Page 99 P15_2 P15_1 P15_0 P16_7 P16_6 P16_5 P16_4 P16_3 P16_2 P16_1 P16_0 P17_7 P17_6 P17_5 P17_4 P17_3 P17_2 P17_1 P17_0 P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 P19_7 P19_6 P19_5 P19_4 P19_3 P19_2 P19_1 P19_0 P20_7 P20_6 P20_5 P20_4 P20_3 P20_2 P20_1 P20_0...
  • Page 100 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions P21_5 P21_4 P21_3 P21_2 P21_1 P21_0 P22_7 P22_6 P22_5 P22_4 P22_3 P22_2 P22_1 P22_0 P23_7 P23_6 P23_5 P23_4 P23_3 P23_2 P23_1 P23_0 P24_7 P24_6 P24_5 P24_4 P24_3 P24_2 P24_1 P24_0 P25_7 P25_6 P25_5 P25_4 P25_3...
  • Page 101 P26_0 P27_7 P27_6 P27_5 P27_4 P27_3 P27_2 P27_1 P27_0 ALARM_1 ALARM_0 P28_7 P28_6 P28_5 P28_4 P28_3 P28_2 P28_1 P28_0 P29_7 P29_6 P29_5 P29_4 P29_3 P29_2 P29_1 P29_0 P30_7 P30_6 P30_5 P30_4 P30_3 P30_2 P30_1 P30_0 P31_7 P31_6 P31_5 P31_4 P31_3 P31_2 P31_1 P31_0...
  • Page 102 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions P32_5 P32_4 P32_3 P32_2 P32_1 P32_0 P33_7 P33_6 P33_5 P33_4 P33_3 P33_2 P33_1 P33_0 P34_7 P34_6 P34_5 P34_4 P34_3 P34_2 P34_1 P34_0 P35_7 P35_6 P35_5 P35_4 P35_3 P35_2 P35_1 P35_0 INITX RSTX HSTX NMIX MD_2...
  • Page 103 ICLK ICD_3 ICD_2 ICD_1 ICD_0 ICS_2 ICS_1 ICS_0 BREAK PLEVEL EXRAM TRSTX TCLK TOEX TWRX TCE1X TADSCX TAD_15 TAD_14 TAD_13 TAD_12 TAD_11 TAD_10 TAD_9 TAD_8 TAD_7 TAD_6 TAD_5 TAD_4 TAD_3 TAD_2 TAD_1 TAD_0 TDT_68 TDT_67 TDT_66 TDT_65 TDT_64 TDT_63 TDT_62 TDT_61 TDT_60 TDT_59...
  • Page 104 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions TDT_56 TDT_55 TDT_54 TDT_53 TDT_52 TDT_51 TDT_50 TDT_49 TDT_48 TDT_47 TDT_46 AU10 TDT_45 AT10 TDT_44 AR10 TDT_43 AT11 TDT_42 AR11 TDT_41 TDT_40 AV10 TDT_39 AU11 TDT_38 AU12 TDT_37 AR12 TDT_36 AT12 TDT_35 AR13 TDT_34 AT13...
  • Page 105 AR18 TDT_11 AV18 TDT_10 AR19 TDT_9 AU19 TDT_8 AT19 TDT_7 AV19 TDT_6 AT20 TDT_5 AV20 TDT_4 AR20 TDT_3 AU20 TDT_2 AR21 TDT_1 AV21 TDT_0 AV22 EMRAM AU21 ECSX AT21 EWRX_3 AU22 EWRX_2 AT22 EWRX_1 AR22 EWRX_0 AR23 EECSX AV23 EEWEX AU23 EEOEX AV24...
  • Page 106 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions AR29 EEA_0 AT29 EED_31 AR30 EED_30 AT30 EED_29 AU31 EED_28 AU32 EED_27 AV31 EED_26 AV32 EED_25 AT31 EED_24 AV33 EED_23 AR32 EED_22 AV34 EED_21 AU33 EED_20 AU34 EED_19 AT32 EED_18 AT33 EED_17 AR33 EED_16 AV35...
  • Page 107 AK37 FLASH_FRSTX VDD5 VDD5 VDD5 VDD5 VDD5 AP11 VDD5 AP19 VDD5 AP23 VDD5 AP31 VDD5 AM35 VDD5 AH34 VDD5 AD34 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VSS5 VSS5 VSS5 VSS5 AJ34 VSS5 AE34 VSS5 AA34 VSS5 VSS5 VSS5 VSS5 VSS5...
  • Page 108 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions HVDD5 HVSS5 HVSS5 HVSS5 AVSS AVRL AVRH5 AVCC5 AVRH3 AVCC3 VDD5R VDD5R VDD5R VDD5R AA38 VCC3C VCC3C VCC3C VCC3C VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VSS3 VSS3...
  • Page 109 AP20 VSS3 AP24 VSS3 AP28 VSS3 AP30 VSS3 AT36 VSS3 AU37 VSS3 AL34 VSS3 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 TS00_0 Chapter 3 MB91460 Series Basic Information 6.Pin Definitions...
  • Page 110: I/O Circuit Type

    Chapter 3 MB91460 Series Basic Information 7.I/O Circuit Type 7. I/O Circuit Type The table below describes the circuit types which are used on the evaluation device MB91V460 Rev.A. Please refer to the datasheets for information about the circuit type of each pin used on the flash devices. Pull Up/ Type Pull Down...
  • Page 111 TE11_0 TE20_0 TE21_0 Dn (ctrl) TE22_0 TS00_0 TS01_0 TS02_0 Chapter 3 MB91460 Series Basic Information Tool Tool Tool Tool VDD 5V 7.I/O Circuit Type 8 mA 4 mA 4 mA 8 mA...
  • Page 112: Pin State Table

    Chapter 3 MB91460 Series Basic Information 8.Pin State Table 8. Pin State Table Explanation of the meaning of words and phrases used in the pin state table according to the chosen mode. • Input enable: It is possible to input a signal to the device. •...
  • Page 113 AD35 P03_7 AC35 P03_6 AB37 P03_5 AC36 P03_4 AA37 P03_3 AB36 P03_2 AD38 P03_1 AC38 P03_0 AB35 AA36 AB38 AA35 MONCL P04_7 P04_6 P04_5 P04_4 P04_3 P04_2 P04_1 P04_0 P05_7 P05_6 P05_5 P05_4 P05_3 P05_2 P05_1 P05_0 P06_7 P06_6 P06_5 P06_4 P06_3 P06_2...
  • Page 114 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P08_7 P08_6 BGRNT P08_5 P08_4 P08_3 WRX3 P08_2 WRX2 P08_1 WRX1 P08_0 WRX0 P09_7 CSX7 P09_6 CSX6 P09_5 CSX5 P09_4 CSX4 P09_3 CSX3 P09_2 CSX2 P09_1 CSX1 P09_0 CSX0 P10_7 P10_6 MCLKE MCLKE P10_5 MCLKI MCLKI /MCLKI P10_4 MCLKO MCLKO /MCLKO...
  • Page 115 P12_7 DEOP3 DEOP3 P12_6 DEOTX3DEOTX3 DEOP3 P12_5 DACKX3 DACKX3 P12_4 DREQ3 DREQ3 P12_3 DEOP2 DEOP2 P12_2 DEOTX2DEOTX2 DEOP2 P12_1 DACKX2 DACKX2 P12_0 DREQ2 DREQ2 P13_7 DEOP1 DEOP1 P13_6 DEOTX1DEOTX1 DEOP1 P13_5 DACKX1 DACKX1 P13_4 DREQ1 DREQ1 P13_3 DEOP0 DEOP0 P13_2 DEOTX0DEOTX0 DEOP0 P13_1 DACKX0 DACKX0 P13_0 DREQ0 DREQ0 ICU7/...
  • Page 116 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P17_7 P17_6 P17_5 P17_4 P17_3 P17_2 P17_1 P17_0 P18_7 P18_6 P18_5 P18_4 P18_3 P18_2 P18_1 P18_0 P19_7 P19_6 P19_5 P19_4 P19_3 P19_2 P19_1 P19_0 P20_7 P20_6 P20_5 P20_4 P20_3 P20_2 P20_1 P20_0 P21_7 P21_6...
  • Page 117 P22_7 SCL1 P22_6 SDA1 P22_5 SCL0 P22_4 SDA0 P22_3 P22_2 P22_1 P22_0 P23_7 P23_6 P23_5 P23_4 P23_3 P23_2 P23_1 P23_0 INT15 Output Hi-Z, Output Hi-Z, INT14 Input Input enabled enabled INT13 INT12 INT11 Output Hi-Z, Output Hi-Z, INT10 Input Input enabled enabled INT9...
  • Page 118 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P24_7 P24_6 P24_5 P24_4 P24_3 P24_2 P24_1 P24_0 P25_7 P25_6 P25_5 P25_4 P25_3 P25_2 P25_1 P25_0 P26_7 P26_6 P26_5 P26_4 P26_3 P26_2 P26_1 P26_0 P27_7 P27_6 P27_5 P27_4 P27_3 P27_2 P27_1 P27_0 ALARM_ ALARM_...
  • Page 119 P29_7 P29_6 P29_5 P29_4 P29_3 P29_2 P29_1 P29_0 P30_7 P30_6 P30_5 P30_4 P30_3 COM3 P30_2 COM2 P30_1 COM1 P30_0 COM0 P31_7 SEG39 P31_6 SEG38 P31_5 SEG37 P31_4 SEG36 P31_3 SEG35 P31_2 SEG34 P31_1 SEG33 P31_0 SEG32 P32_7 SEG31 P32_6 SEG30 SCK15 P32_5 SEG29 SOT15 P32_4...
  • Page 120 Chapter 3 MB91460 Series Basic Information 8.Pin State Table P34_7 P34_6 P34_5 P34_4 P34_3 P34_2 P34_1 P34_0 P35_7 P35_6 P35_5 P35_4 P35_3 P35_2 P35_1 P35_0 INITX RSTX HSTX NMIX MD_2 MD_1 MD_0 SEG15 SEG14 SCK11 SEG13 SOT11 Output Hi-Z, Output Hi-Z, SEG12 SIN11 Input Input...
  • Page 121: Chapter 4 Cpu Architecture

    Chapter 4 CPU Architecture This chapter describes the architecture of FR60 family CPU. 1. Overview The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for embedded application. CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. “32- bit/16-bit bus converter”...
  • Page 122: Features

    Chapter 4 CPU Architecture 2.Features 2. Features ■ Features of internal architecture • RISC architecture • Base instruction: 1 instruction/1 cycle • 32-bit architecture • General-purpose register: 32-bit x 16 • 4GB of linear memory space • Equipped with multiplier. •32-bit x 32-bit multiplication: 5 cycles •16-bit x 16-bit multiplication: 3 cycles •...
  • Page 123: Cpu

    3. CPU The CPU realizes the compact implementation of a 32-bit RISC FR architecture. It employs a 5-stage instruction pipeline method to execute 1 instruction per 1 cycle. This pipeline consists of the following stages. • Instruction fetch (IF): outputs instruction address to fetch instruction. •...
  • Page 124: Instruction Overview

    Chapter 4 CPU Architecture 6.Instruction Overview 6. Instruction Overview The FR60 family supports logic operation, bit operation and direct addressing instruction optimized for embedded application as well as general RISC instruction system. Instruction-set list is shown in the appendix. Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it enables you to generate compact program code.
  • Page 125: Data Structure

    7. Data Structure FR60 has two data allocations as follows. ■ Bit Ordering FR60 uses little endian as bit ordering. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ■...
  • Page 126: Word Alignment

    Chapter 4 CPU Architecture 8.Word Alignment 8. Word Alignment Since instructions and data are accessed by byte, allocated addresses vary by instruction length or data width. ■ Program Access FR60 program is required to be allocated in addresses multiplied by 2. PC's bit0 is cleared for instruction execution upon the PC update.
  • Page 127: Addressing

    9. Addressing Address space is 32-bit linear. ■ Map 0000 0000 0000 0100 0000 0200 0000 0400 000F FC00 000F FFFF FFFF FFFF FR60’s logical address space is 4GB (2 ■ Direct Addressing Area The following areas are used for I/O. These spaces are referred to as direct addressing area where you can specify direct operand address by the instruction.
  • Page 128 Chapter 4 CPU Architecture 9.Addressing...
  • Page 129: Chapter 5 Cpu Registers

    Chapter 5 CPU Registers 1. General-purpose Registers Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and memory access pointers on various operations. Of 16 registers, the following registers are reserved for special application. • R13: Virtual accumulator •...
  • Page 130 Chapter 5 CPU Registers 2.Dedicated Registers 2.1 PC: Program Counter Program Counter (PC) consists of 32 bits. Figure 2-2 Bit Structure of Program Counter (PC) Program counter (PC) indicates active instruction address. Upon the execution of the instruction, program counter (PC)’s bit 0 is cleared. 2.2 PS: Program Status Register Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR and CCR.
  • Page 131 This bit becomes “0” by reset. • [Bit 3] N: Negative flag This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers. It indicates that operation result is positive value. It indicates that operation result is negative value. •...
  • Page 132 Chapter 5 CPU Registers 2.Dedicated Registers program. ■ ILM: Interrupt Level Mask Register Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM) ILM4 • This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask. •...
  • Page 133 ■ Caution: PS Register Since some instructions have already processed PS register in advance, the following exception operations may break interrupt processing routine during the use of debugger, or update PS flag data. In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and after EIT will be processed in accordance with specification.
  • Page 134 Chapter 5 CPU Registers 2.Dedicated Registers 2.3 TBR: Table-base Register Table-base register (TBR) consists of 32 bits. Figure 2-7 Bit Structure of Table-base Register (TBR) Table-base register holds head address of vector table used for EIT processes. Vector address is made by adding offset value specified in TBR and EIT each. 2.4 RP: Return Pointer Return pointer (RP: Return Pointer) consists of 32 bits.
  • Page 135 2.6 USP: User Stack Pointer User Stack Pointer (USP) consists of 32 bits. Figure 2-10 Bit Structure of User Stack Pointer (USP) When S flag is “1”, this pointer works as R15. You can explicitly specify USP. You can not use it for RETI instruction. This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates.
  • Page 136 Chapter 5 CPU Registers 2.Dedicated Registers 2.7 MDH, MDL: Multiply & Divide Register Multiply & Divide register (MDH/MDL) consists of 32 bits. Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL) This is the register for multiplication and division and consists of 32 bits. Initial value by reset is indeterminate.
  • Page 137: Chapter 6 Eit: Exceptions, Interrupts And Traps

    Chapter 6 EIT: Exceptions, Interrupts and Traps 1. Overview EIT means that some events interrupt current program to execute other programs. EIT stands for Exception, Interrupt and Trap. • Exception is the event which is generated in association with active context. It is returned to the instruction which triggered the exception.
  • Page 138: Eit Interrupt Level

    Chapter 6 EIT: Exceptions, Interrupts and Traps 5.EIT Interrupt Level 5. EIT Interrupt Level Interrupt level is between 0 and 31, and controlled with 5 bits. Table 5-1 Interrupt Level of EIT Level Binary Decimal 00000 (Reserved for system) 00011 (Reserved for system) 00100 INTE instruction...
  • Page 139: Multiple Eit Processing

    7. Multiple EIT Processing If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to accept, and then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting EIT, CPU executes instruction of the last accepted EIT handler.
  • Page 140 Chapter 6 EIT: Exceptions, Interrupts and Traps 7.Multiple EIT Processing Main routine Priority (High) Generation of NMI (Middle) Execution of INT instruction (Low) Execution of user interrupt Figure 7-1 Multiple EITs Process INT instruction handler User interrupt handler (2) Second execution (3) Third execution NMI handler (1) First execution...
  • Page 141: Operation

    8. Operation In the following sections, note that source “PC” means instruction address which detected each EIT trigger. Similarly, “address of next instruction” means the following addresses based on the instruction which detected the EIT. • When LDI is 32: PC+6 •...
  • Page 142 Chapter 6 EIT: Exceptions, Interrupts and Traps 8.Operation 8.2 Operation of INT Instruction INT No. u8 instruction is operated as follows. Branches to interrupt handler of vector specified in u8. ■ Operation 1. The contents of the program status (PS) are saved to the system stack. 2.
  • Page 143 8.4 Operation of Step Trace Trap If you set T flag at SCR within PS and enable step trace trap function, step trace trap is generated with each executing instruction. ■ Condition for detecting step trace trap T flag = 1 Instructions are other than delayed branch command.
  • Page 144: Caution

    Chapter 6 EIT: Exceptions, Interrupts and Traps 9.Caution 8.6 Coprocessor Absent Trap If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated. ■ Operation 1. The contents of the program status (PS) are saved to the system stack. 2.
  • Page 145: Chapter 7 Branch Instruction

    Chapter 7 Branch Instruction FR60 can instruct the operation with and without delay slot for branch instruction. 1. Branch Instruction with Delay Slot • Branch instruction with delay slot JMP:D @Ri CALL:D label12 BRA:D label9 BNO:D label9 BC:D label9 BNC:D label9 BV:D label9 BNV:D label9 BLE:D label9...
  • Page 146: Actual Example (With Delay Slot)

    Chapter 7 Branch Instruction 3.Actual Example (with Delay Slot) 3. Actual Example (with Delay Slot) 3.1 JMP:D @Ri / CALL:D @Ri Instruction Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay slot update Ri. •...
  • Page 147: Restrictions On Branch Instruction With Delay Slot

    4. Restrictions on Branch Instruction with Delay Slot 4.1 Available Instructions for Delay Slot Instructions which meet the following requirements can only be executed in delay slot. • 1-cycle instruction • Non-branch instruction • Instruction which does not affect any operation even if its sequence is changed. “1-cycle instruction”...
  • Page 148: Branch Instruction Without Delay Slot

    Chapter 7 Branch Instruction 5.Branch Instruction without Delay Slot 5. Branch Instruction without Delay Slot • Branch instruction without delay slot: JMP @Ri BRA label9 BC label9 BV label9 BLE label9 6. Operation of Branch Instruction without Delay Slot Operation without delay slot executes instructions in the order of instructions and never executes the instruction located in the next address where a branch instruction exists before branch.
  • Page 149: Chapter 8 Device State Transition

    Chapter 8 Device State Transition 1. Overview MB91460 basically has devices state and flow as shown below. For more information, see “3. State Transition Diagram (Page Power-on INITX INT-pin input 2. Features ■ Device state • RUN (Normal operation): State where the program is executed. •...
  • Page 150: State Transition Diagram

    Chapter 8 Device State Transition 3.State Transition Diagram 3. State Transition Diagram This section describes state transition. Figure 3-1 State Transition of MB91460 Series INIT pin = 0 (INIT) INIT pin = 1 (Cancel of INIT) Termination of oscillation-stabilization wait Cancel of reset (RST) Software reset (RST) Sleep (Writing instruction)
  • Page 151 3.1 RUN (Normal Operation) This is the state where program is executed with all clocks and all circuits are enabled. This state has various paths for a state transition. However, if the synchronous reset mode is selected the state transition operations for some requests are different from normal reset mode. For more information, see the chapter of “Chapter 9 Reset (Page 3.2 SLEEP...
  • Page 152 Chapter 8 Device State Transition 3.State Transition Diagram 3.5 Oscillation-stabilization-wait Reset This is the state where the device is stopped. This state is entered upon a setting-initialization reset (INIT). All internal circuits are stopped except for clock generation control parts (timebase counter and device state control parts).
  • Page 153 Chapter 8 Device State Transition 3.State Transition Diagram...
  • Page 154 Chapter 8 Device State Transition 3.State Transition Diagram...
  • Page 155: Chapter 9 Reset

    Chapter 9 Reset 1. Overview When a reset is triggered, the device halts the program and all hardware operation, and then initializes all states. This state is called a reset. When the reset trigger condition is removed, the device changes from this initialized state to restart the program and hardware operation.
  • Page 156: Configuration

    Chapter 9 Reset 3.Configuration • A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillation stabilization time elapses. 3. Configuration State transition control circuit (reset related) OSCD1 STCR: bit1 STCR: bit1 Main clock continues to operate during stop mode Main clock halts during stop mode STCR: bit0 STCR: bit0...
  • Page 157: Registers

    4. Registers 4.1 RSRR: Reset Cause Register Stores the cause of the previous reset, and sets the period and activation control for the watchdog timer. • RSRR: Address 0480h (Access: Byte, Half-word) INIT HSTB WDOG R/WX R/WX R/WX Note: See “Meaning of Bit Attribute Symbols (Page Reading the reset request cause returns the reset cause flags and then clears the flag values to “0”.
  • Page 158 Chapter 9 Reset 4.Registers Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST). SRST No RST has been triggered by a software reset. RST has been triggered by a software reset. The software reset occurred flag (SRST) is cleared to “0” after reading. •...
  • Page 159 4.2 STCR: Standby Control Register This register is used for software reset control (changing to standby mode, pin control in stop mode, and clock oscillation halted in stop mode), and specifies the oscillation stabilization wait time. Note: See also “Chapter 10 Standby (Page •...
  • Page 160 Chapter 9 Reset 4.Registers 4.3 MOD: Mode Pins These pins specify the location of the mode vector and reset vector that are read after the MCU is reset. Mode pins Mode name MD2 MD1 Internal ROM mode External ROM mode 4.4 Mode Vector The data written to the mode register (MODR) by the mode vector fetch operation is called the mode data.
  • Page 161 Initial value to load into PC. Mode 000FFFF8 XXXXXXXX XXXXXXXX XXXXXXXX Vector Reset 000FFFFC Vector 4.6 Device Mode Overview The following table gives an overview about supported device mode combinations on the MB91460 series: Mode pins Mode/Reset Vector MD2 MD1 MD0 access area Internal External...
  • Page 162: Init Pin Input (Init: Settings Initialization Reset)

    Chapter 9 Reset 5.INIT Pin Input (INIT: Settings Initialization Reset) 5. INIT Pin Input (INIT: Settings Initialization Reset) 5.1 Trigger The pin is used to trigger a settings initialization reset. A settings initialization reset (INIT) request remains active while the pin remains at the “L” level. Keep the “L”...
  • Page 163 5.6 Reset Cancellation Sequence After the cancellation (removal) of the settings initialization reset (external INITX pin) request the device performs the following operations in the sequence listed. 1. Removal of settings initialization reset (INIT) 2. Set operation reset (RST) state and start internal clock 3.
  • Page 164: Watchdog Reset (Init: Settings Initialization Reset)

    Chapter 9 Reset 6.Watchdog Reset (INIT: Settings Initialization Reset) 6. Watchdog Reset (INIT: Settings Initialization Reset) 6.1 Trigger Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a watchdog reset request is generated unless “A5 delay register (WPR) within the time specified by the watchdog period selection bits (RSRR.WT[1:0]).
  • Page 165: Software Reset (Rst: Operation Initialization Reset)

    7. Software Reset (RST: Operation Initialization Reset) 7.1 Trigger Writing “0” to the software reset bit (STCR.SRST) generates a software reset request. A software reset requests an operation reset (RST). 7.2 Releasing the Reset Request The software reset request is released after the request is received and the operation reset (RST) generated. 7.3 Flag When software reset request triggers an operation reset (RST), the software reset flag (RSRR.SRST) is set to “1”.
  • Page 166: Reset Operation Modes

    Chapter 9 Reset 8.Reset Operation Modes 8. Reset Operation Modes The following two different modes can be used for an operation reset (RST): • Normal (asynchronous) reset mode • Synchronous reset mode Which mode to use is specified by the synchronous reset operation enable bit (TBCR.SYNCR). Pin input resets and watchdog resets always use normal reset mode.
  • Page 167: Mcu Operation Mode

    9. MCU Operation Mode After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data. Operation mode Bus mode Access mode 9.1 Bus Modes and Access Modes ■ Bus mode The bus mode controls internal ROM operation and the external access function. The bus mode is specified by the mode setting pins (MD2, MD1, MD0) and internal ROM enable bit (Mode-Vector.
  • Page 168: Caution

    Chapter 9 Reset 10.Caution 10. Caution • INIT pin input Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also, after turning on the power, ensure a sufficient oscillation stabilization wait time is provided for the oscillation circuit by holding the input to the pin at the “L”...
  • Page 169 Chapter 9 Reset 10.Caution...
  • Page 170 Chapter 9 Reset 10.Caution...
  • Page 171: Chapter 10 Standby

    Chapter 10 Standby 1. Overview Two standby modes (low power consumption modes) are available. • Sleep mode: Stops the program • Stop mode: Shuts down the device Note: It is possible to keep the Real Time Clock active in STOP mode (see chapter RTC). 2.
  • Page 172: Configuration

    Chapter 10 Standby 3.Configuration 3. Configuration SYNCS TB CR: bit0 Setting prohibited Synchronous standby OSCD1 STCR: bit0 Do not halt main clock oscillation during stop mode. Halt main clock oscillation during stop mode. STCR: bit5 Maintain same states during stop mode. Set pins to high impedance during stop mode.
  • Page 173: Registers

    4. Registers 4.1 STCR: Standby Control Register Used to control transition to the stop and sleep standby modes, and to specify the pin states and whether to halt the oscillation during stop mode. Note: See “Chapter 9 Reset (Page • STCR: Address 0481h (Access: Byte) STOP SLEEP (See...
  • Page 174 Chapter 10 Standby 4.Registers • Bit0: Main clock oscillation halt OSCD1 4.2 TBCR: Timebase timer control register This register controls the timebase timer interrupts and the options for resets and standby operation. Note: See also “Chapter 19 Timebase Timer (Page •...
  • Page 175: Operation

    5. Operation 5.1 Sleep Mode ■ Entering sleep mode Writing “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode. The device remains in this mode until an event occurs to wakeup the device from sleep mode. (See “8. Caution (Page No.165)”.) ■...
  • Page 176 Chapter 10 Standby 5.Operation 5.2 Stop mode ■ Entering stop mode Writing “1” to the stop mode bit (STCR.STOP) changes to stop mode. The device remains in this mode until an event occurs to wakeup the device from stop mode. (See “8.
  • Page 177: Settings

    6. Settings Table 6-1 Settings Required to Change to Sleep Mode Setting Interrupt settings Synchronous standby settings Change to sleep mode Operational restrictions *:For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings Required to Change to Stop Mode Setting Selects the oscillation stabilization wait time...
  • Page 178 Chapter 10 Standby 7.Q&A 7.2 How do I change to stop mode? • When operating on the main PLL clock, the operating clock must be set to the main clock divided by two. “7.3 How do I select the operating clock source? (Page the operating clock.
  • Page 179 7.6 How do I recover from stop mode? The following events end stop mode: • The following four interrupts change the device to the oscillation stabilization wait state. • External level-detect interrupt or edge-detect interrupt. • Oscillation stabilization wait timer for the main clock when oscillation not halted. •...
  • Page 180 Chapter 10 Standby 7.Q&A...
  • Page 181: Caution

    8. Caution • Points to note when changing to sleep mode When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”). Also, in order to change to sleep mode with synchronous standby operation enabled, the STCR register must be read after writing to the SLEEP bit.
  • Page 182 Chapter 10 Standby 8.Caution...
  • Page 183: Chapter 11 Memory Controller

    Chapter 11 Memory Controller 1. Overview This module combines the interfaces to the F-Bus memory resources, FLASH and General Purpose RAM (also ref- erenced as I/D-RAM). These memories can be combined CODE and DATA storage. While code fetch is possible in general via the F-Bus at the FR core, due to performance reasons the code fetch is accellerated by a direct I-Bus connection in MB91460 series MCUs.
  • Page 184: Registers

    Chapter 11 Memory Controller 7.Registers • Reset vector address: 0x000ffffc; return 0x00030000 at RAM execution mode (jump to test pro- gram) or return 0x0000bff8 in any other case (jump to Boot ROM) • If FMCS_FIXE is switched off, the FLASH memory can be accessed on addresses 0x000ffff8 and 0x000ffffc.
  • Page 185: Explanations Of Registers

    8. Explanations of Registers ● FLASH Interface Control Register Control Register byte 0 Address : 7000 Read/write ⇒ (R/W) (R/W) (R/W) (R) Default value⇒ Control Register byte 1 Address : 7001 Read/write ⇒ Default value⇒ Control Register byte 2 Address : 7002 Read/write ⇒...
  • Page 186 Chapter 11 Memory Controller 8.Explanations of Registers • BIT[29]: BIRE - Burn-In ROM Enable Disable Burn-In ROM and enable FLASH access at Burn-In ROM address Enable access to the Burn-In ROM (default) The BIRE bit is a reserved bit and should not be used. •...
  • Page 187 It is recommended to always refer to the setting requirements of ATDIN, EQIN and waitcycles for each product which are provided by Fujitsu (see the related datasheets). (PHASE setting is not available on MB91460 series) Chapter 11 Memory Controller 8.Explanations of Registers...
  • Page 188 Some embedded FLASH memories supports switching the 64 bit read mode to increase the access per- formance. Please contact Fujitsu if this feature is available on the product you are using. This bit is cleared after reset. The 32 bit read and write access to the FLASH memory is enabled by de- fault.
  • Page 189 • BIT[7]: FLUSH - Flush instruction cache entries Flushing the instruction cache entries has been completed Actually flushing the instruction cache entries This bit is set after reset. If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is disabled.
  • Page 190 Chapter 11 Memory Controller 8.Explanations of Registers • BIT[4]: PFMC - Prefetch Miss Cache enable Standard cache algorithm (default) Prefetch misses are cached only This bit is cleared after reset. The prefetch miss cache is disabled by default. The instruction cache uses the stand- ard algorithm of writing cache entries for each accessed instruction word from FLASH.
  • Page 191 • BIT[1:0]: SZ[1:0] - Cache size configuration 0kByte - Cache disabled 4kByte (1024 entries) 8kByte (2048 entries) 16kByte (4096 entries) (default) The cache size is set to ’11’ after reset. The cache size can be configured on the evaluation device (EVA). Remark: The number of cache entries determines the TAG initialization period at device startup, see the explanai- tion of the FLUSH bit above.
  • Page 192 Chapter 11 Memory Controller 8.Explanations of Registers WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP configuration is in units of clock cycles. The value of WTP should be set to the intra page access time (cycle time) of the FLASH memory in number of clock cycles, subtracted by one.
  • Page 193 FLASH access cycle waveform flash_start ATDIN EQIN flash_wait tATD Figure 8-1 Timing of a FLASH access cycle Figure shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for this example.
  • Page 194 Chapter 11 Memory Controller 8.Explanations of Registers ● FLASH Memory Adddress Check register (FMAC) Address 7008 -------- This register captures the address at the begin of a FLASH access cycle for test purposes. The register could be read only. ● Non-cacheable area definition The non-cacheable area definition registers FCHA0 and FCHA1 define the FLASH region not to be cached.
  • Page 195: Chapter 12 Instruction Cache

    Chapter 12 Instruction Cache This chapter describes the instruction cache memory included in MB91460 family members and its operation. 1. General description The instruction cache is a fast local memory for temporary storage. Once an instruction is accessed to be fetched from external slower memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on.
  • Page 196 Chapter 12 Instruction Cache 2.Main body structure Way 1 Way 2 [Bits 31 to 9] Address tag This area stores the upper 23 bits of the memory address of the instruction cached in the corresponding block. For example, memory address IA of the instruction data stored in sub- block k in block i is obtained from the following equation: IA = address tag x 2 The address tag is used to check for a match with the instruction address requested for...
  • Page 197 FLUSHbit is set to "0" when the cache is flushed.) [Bit 1] LRU bit (way 1 only) This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed.
  • Page 198 Chapter 12 Instruction Cache 2.Main body structure [Bit 7] RAM: RAM Mode Setting this bit to "1" causes the cache to operate in RAM mode. By placing the cache in RAM mode, the cache RAM is mapped as shown in Figure I-CACHE-3 while the cache is enabled with the ENAB bit set to "1".
  • Page 199 Chapter 12 Instruction Cache 2.Main body structure Figure 2-3 I-Cache Address Map...
  • Page 200 Chapter 12 Instruction Cache 2.Main body structure Figure 2-4 I-Cacheable Area...
  • Page 201: Operating Mode Conditions

    3. Operating mode conditions ● Cache status in various operating modes The table below indicates the prevailing state for disable and flush when the associated bit is changed by bit manipulation instruction, etc. Immediately after a Reset Contents Cache Memory undefined Address Contents...
  • Page 202: Cacheable Areas In The Instruction Cache

    Chapter 12 Instruction Cache 4.Cacheable areas in the instruction cache ● Cache Entry Update Cache entries are updated as shown in the following table. Not updated Miss The memory data is loaded, and the cache entry data is updated. 4. Cacheable areas in the instruction cache •...
  • Page 203 To disable the I-Cache, set the ENAB bit to 0. Idi #0x000003e7,r0 Idi #0B00000000,r1 stb r1,@r0 In the resultant state (same as state prevailing after reset), there appears to be no cache. The cache can be turned off if the processing may experience problems due to cache overhead Locking all cached instructions To lock all the currently-cached instructions in the I-Cache, set the register GBLK bit to 1.
  • Page 204 Chapter 12 Instruction Cache 5.Settings for handling the I-Cache Only lock information is released; locked instructions are replaced sequentially with new instructions according to the state of the LRU bit.
  • Page 205: Chapter 13 Clock Control

    Chapter 13 Clock Control 1. Overview The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator. The circuit supports a range of clock speeds from the high speed clock (100MHz maximum) to the low speed clock (32.768kHz).
  • Page 206: Configuration

    Chapter 13 Clock Control 3.Configuration • External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16 The clock used by the external bus expansion interface. The circuits that use this clock are as follows. • External bus expansion interface •...
  • Page 207: Registers

    4. Registers 4.1 CLKR: Clock Source Control Register Selects the clock source for the base clock used to run the MCU and controls the PLL. • CLKR: Address 0484h (Access: Byte) R/W0 R/W0 R/W0 (See “Meaning of Bit Attribute Symbols (Page •...
  • Page 208 Chapter 13 Clock Control 4.Registers • After setting “11B” (subclock), insert one or more NOP instructions. • Selecting the subclock as the clock source is prohibited while the subclock selection enable bit (SCKEN) is “0”. (See table for details.) Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified Modify permitted “00”...
  • Page 209 4.2 DIV0R: Clock Division Setting Register 0 Sets the division ratio for the clocks used for internal device operation. DIVR0: Address 0486h (Access: Byte, Half-word) (See “Meaning of Bit Attribute Symbols (Page • Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and peripheral bus (CLKP).
  • Page 210 Chapter 13 Clock Control 4.Registers 1010 1011 1100 1101 1110 1111 • Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP). The 16 options listed in the table are available. • Do not set a division ratio that exceeds the maximum operating frequency of the MCU. Φ/11 Φ/12 Φ/13...
  • Page 211 4.3 DIV1R: Clock Division Setting Register 1 Sets the division ratio for the clocks used for internal device operation. • DIVR1: Address 0487h (Access: Byte, Half-word) (See “Meaning of Bit Attribute Symbols (Page Sets the clock division ratio (relative to the base clock) for the clock used by the external bus interface (CLKT). •...
  • Page 212 Chapter 13 Clock Control 4.Registers 4.4 CSCFG: Clock Source Configuration Register This register controls the main clock oscillation in subclock mode • CSCFG: Address 04AEh (Access: Byte) EDSUEN PLLLOCK RCSEL (See “Meaning of Bit Attribute Symbols (Page • bit7: EDSU/MPU Enable EDSUEN EDSU/MPU is (clock) disabled [Initial value] EDSU/MPU is (clock) enabled...
  • Page 213 Chapter 13 Clock Control 4.Registers -1-- Subclock Calibration is sourced by RC Oscillation 0--- LCD Controller is sourced by Sub Oscillation 1--- LCD Controller is sourced by RC Oscillation...
  • Page 214 Chapter 13 Clock Control 4.Registers 4.5 OSCCR: Oscillation Control Register This register controls the main clock oscillation in subclock mode • OSCCR: Address 04CCh (Access: Byte) – – – RX/WX RX/WX RX/WX (See “Meaning of Bit Attribute Symbols (Page • bit7-2: Undefined bit Writing does not affect the operation.
  • Page 215: Operation

    5. Operation This section describes how to setup and switch between clocks. 5.1 Clock Setup Sequence (Example) Setup operating clocks. Setup base clock. 5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example) (1) Select sub clock mode. (2) Halt main PLL (PLL1EN = "0"), halt main clock oscillation (OSCDS1 = "0") Sub clock mode with main clock...
  • Page 216 Chapter 13 Clock Control 5.Operation 5.3 Notes ■ Main PLL control After initialization, the main PLL oscillation is halted. While halted, the output of the main PLL cannot be selected as the clock source. After the program starts, first set the multiplier for the main PLL that you want to use as the clock source and then, after allowing a time for the main PLL to lock, change the clock source.
  • Page 217: Settings

    6. Settings Table 6-1 Settings for Operating at 1/2 of the Main Clock Setting Clock source selection *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings for Operating Using the Main PLL Setting Main PLL operation enable Clock source selection *: For the setting procedure, refer to the section indicated by the number.
  • Page 218 Chapter 13 Clock Control 7.Q & A 7. Q & A 7.1 How do I enable or disable clock operation? • There is no operation enable bit for the main clock. Main clock operation is always enabled. (Halting the oscillation in subclock mode or stop mode is handled separately.) •...
  • Page 219 7.4 How do I set the operation clock division ratios? • CPU clock setting The CPU clock setting is set using the CLKB division ratio selection bits (DIVR0.B[3:0]). PLL multiplier ratio To select no division To select divide by 2 To select divide by 3 To select divide by 4 To select divide by 5...
  • Page 220 Chapter 13 Clock Control 7.Q & A 7.5 How do I halt the main clock in sub clock mode? Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS1). Operation in subclock mode To not halt the main clock To halt the main clock (See “8.
  • Page 221: Caution

    8. Caution • Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division ratio setting result in a frequency that exceeds the maximum. • Take care with the sequence in which you set or modify the clock source selection. •...
  • Page 222 Chapter 13 Clock Control 8.Caution...
  • Page 223: Chapter 14 Pll Interface

    Chapter 14 PLL Interface 1. Overview • This blockdiagram (simplified) shows the integration of the PLL and the PLL Interface with the multiplier control logic (1/M, 1/N for basic frequency multiplication and 1/G for clock auto gear). Interface MAIN Osc. Phase Correction 2.
  • Page 224: Registers

    Chapter 14 PLL Interface 4.Registers 4. Registers 4.1 PLL Control Registers Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function. • PLLDIVM: Address 048Ch (Access: Byte, Halfword, Word) R0/W0 R0/W0 R0/W0 (See “Meaning of Bit Attribute Symbols (Page •...
  • Page 225 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bits.The read value is always “0”. • Bit5-0: PLL divide-by-N selection DVN5-DVN0 000000 000001 000010 000011 000100 000101 000110 000111 111111 (Note) The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”). (Note) It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.
  • Page 226 Chapter 14 PLL Interface 4.Registers • PLLMULG: Address 048Fh (Access: Byte, Halfword, Word) MLG7 MLG6 MLG5 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bitThe read value is always “0”. • Bit5-0: PLL auto gear divide-by-G step multiplier selection MLG5-MLG0 00000000 00000001...
  • Page 227 • While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G counter reaches the programmed end value. • This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect. •...
  • Page 228: Recommended Settings

    Chapter 14 PLL Interface 5.Recommended Settings 5. Recommended Settings PLL Input Frequency Parameter (CK) DIVM [MHz] • Important remark: Not all settings which are shown in this table are available for all devices. Please consult the available datasheet for each device for the maximum allowed PLL output and the allowed maximum frequencies for each clock domain (CLKB, CLKP and CLKT) respectively.
  • Page 229: Clock Auto Gear Up/Down

    6. Clock Auto Gear Up/Down To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/ DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL interface. The main functionality is implemented using two divide-by counters (divide-by-M and divide-by-G counter), where one supplies the PLL feedback always with the target frequency (divide-by-M counter), and the other (divide-by-G counter) which increases the frequency from a programmable frequency divi-...
  • Page 230 Chapter 14 PLL Interface 6.Clock Auto Gear Up/Down this equals to (resolved closed arithmetic series of the first sum term): duration with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout) For the above given setting this equals 1483 PLL output clock cycles with a duration from the start fre- quency to the target frequency of 9262500 ps (about 9.3 us).
  • Page 231: Caution

    7. Caution When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear down flags (PLLCTRL.GRUP, PLLCTRL.GRDN) to evaluate the current state of this function to avoid malfunctions in the clock system due to setting changes prior to completion. Procedure example: •...
  • Page 232 Chapter 14 PLL Interface 7.Caution...
  • Page 233: Chapter 15 Can Clock Prescaler

    Chapter 15 CAN Clock Prescaler 1. Overview • This blockdiagram (simplified) shows the integration of the CAN and the CAN Interface with the CAN clock prescaler logic (1/C) and clock source selector. MAIN Osc. Clock Unit • Remark: If the CLKCAN source is set either to main oscillator or to PLL output then the clock for the CAN is not influenced by the clock modulation.
  • Page 234: Registers

    Chapter 15 CAN Clock Prescaler 3.Registers 3. Registers 3.1 CAN Clock Control Register Controls the CAN clock source, the clock division ratio and the clock disable. • CANPRE: Address 04C0h (Access: Byte) CPCKS1 CPCKS0 R0/W0 R0/W0 (See “Meaning of Bit Attribute Symbols (Page •...
  • Page 235 R/W0 R/W0 (See “Meaning of Bit Attribute Symbols (Page • Bit7-6: Reserved bitAlways write “0” to these register bits. • Bit5-0: CAN clock disable CANCKD5-CANCKD0 -----0 -----1 ----0- ----1- ---0-- ---1-- --0--- --1--- -0---- -1---- 0----- 1----- No.10)” for details of the attributes.) Function CAN controller 0 is enabled CAN controller 0 is disabled...
  • Page 236 Chapter 15 CAN Clock Prescaler 3.Registers...
  • Page 237: Chapter 16 Clock Supervisor

    Chapter 16 Clock Supervisor 1.Overview Clock Supervisor Chapter 16 Clock Supervisor This section gives an overview of the Clock Supervisor. Purpose of the Clock Supervisor is the supervision of the main and sub oscillation clock. In case of main oscillation clock failure the Clock Supervisor control logic will take action, i.e.
  • Page 238: Clock Supervisor Register

    Chapter 16 Clock Supervisor 2.Clock Supervisor Register 2. Clock Supervisor Register This section lists the Clock Supervisor Control Register and describes the function of each bit in detail. ■ Clock Supervisor Control Register (CSVCR) The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor. shows the configuration of the Clock Supervisor Control Register.
  • Page 239 Table 2-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR). Table 2-1 Functional Description of each bit of the Clock Supervisor Control Register Name SCKS (Sub-clock select) (Main clock missing) (Sub-clock missing) (RC-oscillator enable) MSVE (Main clock supervisor...
  • Page 240: Block Diagram Clock Supervisor

    Chapter 16 Clock Supervisor 3.Block Diagram Clock Supervisor 3. Block Diagram Clock Supervisor This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock Supervisor are: l Main Clock Supervisor l Sub-Clock Supervisor l Control Logic l RC-Oscillator ■...
  • Page 241: Operation Modes

    4. Operation Modes This section describes all operation modes of the Clock Supervisor. ■ Operation mode with initial settings In case the clock supervisor control register (CSVCR) is not configured at the beginning of the user program, the RC-oscillator, the main clock supervisor and the sub-clock supervisor is enabled. •...
  • Page 242 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-1 Timing Diagram: Initial settings, main clock missing during power-on reset PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
  • Page 243 Figure 4-2 Timing Diagram: Initial settings, main clock missing during ’oscillation stabilisation wait time’ PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Chapter 16 Clock Supervisor 4.Operation Modes...
  • Page 244 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-3 Timing Diagram: Initial settings, main clock missing after ’oscillation stabilisation wait time’ PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
  • Page 245 Figure 4-4 Timing Diagram: Initial settings, sub-clock missing before timeout PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Chapter 16 Clock Supervisor 4.Operation Modes...
  • Page 246 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-5 Timing Diagram: Initial settings, sub-clock missing after timeout PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING...
  • Page 247 ■ Disabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and main clock or sub-clock supervisor is enabled. • The RC-oscillator can be disabled by setting bit RCE (bit 4 of CSVCR) to ’0’. First disable the main clock and sub-clock supervisor.
  • Page 248 Chapter 16 Clock Supervisor 4.Operation Modes ■ Re-enabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and both main clock and sub-clock supervisor are disabled. • The RC-oscillator can be enabled by setting RCE (bit 4 of CSVCR) to ’1’. •...
  • Page 249 ■ Sub-clock modes The main clock supervisor is automatically disabled in sub-clock modes. The enable bit MSVE remains unchanged. At transition from sub-clock mode to main clock mode the main clock supervisor is enabled after the ’oscillation stabilisation wait time’ with the rising edge of signal OSC_STAB or in case the main clock is missing before the completion of the ’oscillation stabilisation wait time’, after the ’main clock timeout’...
  • Page 250 Chapter 16 Clock Supervisor 4.Operation Modes Figure 4-9 Timing Diagram: Sub-clock missing in main clock mode, SRST=1 PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Clock Mode Main Main...
  • Page 251 Figure 4-10 Timing Diagram: Waking up from sub-clock mode PONR MCLK SCLK RC_CLK OSC_STAB TO_MCLK TO_SCLK MSVE MSEN SSVE SSEN MCLK_STBY SCLK_STBY SRST EXT_RST EXT_RST_OUT MCLK_OUT SCLK_OUT MCLK_MISSING SCLK_MISSING Main Clock Mode Main Chapter 16 Clock Supervisor 4.Operation Modes...
  • Page 252: Stop Mode

    Chapter 16 Clock Supervisor 4.Operation Modes ■ Stop mode RC-oscillator, main clock and sub-clock supervisors are enabled, they will be automatically disabled at transition into stop mode. The corresponding enable bits in the clock supervisor control register remain unchanged. So after wake-up from stop mode the RC-oscillator and the clock supervisors will be enabled again. If the corresponding enable bits are set to ’0’, the RC-oscillator and the clock supervisors will stay disabled after wake-up from stop mode.
  • Page 253 ■ Operation with single clock device In a single clock device the sub-clock supervisor can provide the RC-oscillation clock as sub-clock. To enable this feature, SCKS bit (bit7 of CSVCR) must be set to ’1’ (refer to Table 2-1for precautions when modifying this bit) and SRST must be ’0’...
  • Page 254 Chapter 16 Clock Supervisor 4.Operation Modes ■ Check if reset was asserted by the Clock Supervisor To find out whether the Clock Supervisor has asserted reset , the software must check the reset cause by reading the WDTC register at address A8 .
  • Page 255: Chapter 17 Clock Modulator

    Chapter 17 Clock Modulator 1.Overview Chapter 17 Clock Modulator This chapter provides an overview of the Clock Modulator and its features. It describes the reg- ister structure and operation of the Clock Modulator. 1. Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies.
  • Page 256: Clock Modulator Registers

    Chapter 17 Clock Modulator 2.Clock Modulator Registers 2. Clock Modulator Registers This section lists the clock modulator registers and describes the function of each register in de- tail. ● Clock modulator registers Figure 2-1 Clock modulator registers CMPRL (lower) Address: 0004B9 Initial value 1 1 1 1 1 1 0 1...
  • Page 257 ● Clock Modulator Control Register (CMCR) The Control Register (CMCR) has the following functions: Set the modulator to power down mode Modulator enable/disable in frequency modulation mode Indicates the status of the modulator Figure 2-2 Configuration of the clock modulator control register (CMCR) 0004BB served served...
  • Page 258 Chapter 17 Clock Modulator 2.Clock Modulat