Register Of Clock Generation Controller - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.12.6 Register of Clock Generation Controller

This section describes the functions of registers to be used in the clock generation
controller.
■ Reset Source Register/Watchdog Timer Control Register (RSRR)
Figure 3.12-2 shows the configuration of the reset source register/watchdog timer control
register (RSRR).
Figure 3.12-2 Reset Source Register/Watchdog Timer Control Register (RSRR)
Address: 00000480
Initial value (INIT pin)
Initial value (INIT)
Initial value (RST)
−: Varies according to the source.
x: Not initialized
This register holds the source of the last reset that occurred as well as the interval setting and
startup control for the watchdog timer. If the timer is read, the reset source that has been held is
cleared after it is read. If more than one reset is generated before this register is read, reset
source flags are accumulated and the multiple flags are set.
Writing to this register starts the watchdog timer. Thereafter, the watchdog timer continues
running until a reset (RST) occurs.
The following describes the functions of the reset source register/watchdog timer control register
(RSRR) bits.
[bit15] INIT (INITialize reset occurred)
This bit indicates whether a reset (INIT) occurred due to INIT pin input.
Table 3.12-1 INIT Function
INIT
0
1
• This bit is initialized to "0" after it is read.
• This bit is readable; writing to the bit has no effect on the bit value.
[bit14] (Reserved)
This bit is reserved.
110
bit 15 14 13
INIT - WDOG
H
R R R
1 0 0
− −
0
X X X
No reset (INIT) occurred due to INIT pin input.
A reset (INIT) occurred due to INIT pin input.
12 11 10 9
- SRST - WT1
R R R R/W
0 0 0 0
−
X X 0
− −
X 0
Function
8
WT0
R/W
0
0
0