2-Cycle Transfer (Internal Ram -> External I/O, Ram) - Fujitsu FR60 Hardware Manual

4.10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)
This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation.
The timing is the same as for external I/O, RAM -> internal RAM.
■ 2-Cycle Transfer (Internal RAM -> External I/O, RAM)
Figure 4.10-8 shows the operation timing chart for (TYP3 to TYP0=0000
IOWR=00
Figure 4.10-8 shows a case in which a wait is not set on the I/O side.
Figure 4.10-8 Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)
FR30
compatible
mode
• The bus is accessed in the same way as an interface when DMAC transfer is not performed.
• DACKn/DEOPn is not output in the internal RAM access cycles.
).
H
MCLK
A31 to A00
AS
CSn
(I/O side)
WRn
D31 to D00
DACKn
DEOPn
DACKn
Basic
mode
DEOPn
DREQn
CHAPTER 4 EXTERNAL BUS INTERFACE
I/O address
, AWR=0008 ,
B H
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