Control Status Register (Adcs) - Fujitsu FR60 Hardware Manual

12.2.1 Control Status Register (ADCS)

The control status register (ADCS) controls the A/D converter and displays its status.
■ Bit Configuration of Control Status Register (ADCS)
Figure 12.2-2 shows the bit configuration of the control status register (ADCS).
Figure 12.2-2 Bit Configuration of the Control Status Register (ADCS)
Address: 00007A
Note:
Do not rewrite the control status register (ADCS) while the A/D conversion is in progress, except for
STRT bit and BUSY bit.
■ Detailed Bit of Control Status Register (ADCS)
The following describes the bit functions of the control status register (ADCS).
[bit15] BUSY (BUSY flag and stop)
This bit has the following different functions during reading and writing:
• Reading:
This bit indicates whether the A/D converter is operating. It is set when A/D conversion starts
and cleared when it ends.
• Writing:
Write "0" to this bit during A/D operation to forcibly terminate operation. Use this bit for
forcible termination in continuous mode and stop mode.
"1" cannot be written to the bit that indicates whether the A/D converter is operating. For a read
by a RMW instruction, "1" is read. In single-shot mode, this bit is cleared when A/D conversion
ends. In continuous mode and stop mode, this bit is not cleared until "0" is written to terminate
operation.
This bit is initialized to "0" by a reset.
Do not forcibly terminate operation and start software at the same time (BUSY=0, STRT=1).
[bit14] INT (INTerrupt): Data display
It is set when conversion data is written to the ADCR. (It is when a conversion ends single
conversion mode or when conversion of all channels ends in scan conversion mode.)
If this bit is set while INTE (bit13) is set to "1", an interrupt request occurs. If start of DMA
transfer has been selected, DMA is started. Writing "1" to this bit is meaningless.
This bit is cleared if "0" is written to it or a clear signal from DMAC is received.
bit 15 14 13
BUSY INT INTE
H
R/W R/W R/W
bit 7 6 5
MD1 MD0 ANS2
R/W R/W R/W
CHAPTER 12 A/D CONVERTER
12 11 10
CRF STS1 STS0 STRT
R R/W R/W R/W
4 3 2
ANS1 ANS0 ANE2 ANE1
R/W R/W R/W R/W
9 8 Initial value
00000000
-
B
R/W
1 0 Initial value
00000000
ANE0
B
R/W
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