Block Diagram Of Clock Generation Section; Fig. 4.2 Block Diagram Of Clock Generation Section - Fujitsu MB90420/5 (A) Series Hardware Manual

4.2 Block Diagram of Clock Generation Section

The clock generation section consists of the following five blocks.
• System clock generator
• PLL Multiplying circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
n Block diagram of clock generator
Figure 4.2 gives the block diagram of the clock generation section.
It also includes the standby controller and time-base timer circuit.
Standby controller
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST
Reset
Interrupt
Sub-clock
4-divided
clock
PLL Multiplying circuit
X0A
Pin
X1A
Pin
Clock generation circuit
X0
Pin
X1 Pin
Clock generation circuit
CG1 CG0
RESV RESV
2
S Q
S Q R
S Q
R
R
Clock selector
SCM MCM WS1 WS0 SCS MCS CS0 CS1
Clock select register (CKSCR)
Main clock
512-
2-divided
divided
clock
clock
Oscillation
clock
Time-base timer

Fig. 4.2 Block Diagram of Clock Generation Section

CLOCK
CPU Intermittent
operation cycle selector
Stop, sleep signal
CPU Clock
control circuit
Resource clock
control circuit
Machine
clock
2
2
4-divided 2-divided 2-divided
clock clock clock
4-5
CPU operating
clock
Stop signal
Resource function
operating clock
Oscillation stabilization
wait time selector
2-divided 2-divided 2-divided
clock clock clock
To watchdog timer
4-divided
clock