Block Diagram Of The Clock Generation Control Unit - Fujitsu MB91260B Series Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.11.5

Block Diagram of the Clock Generation Control Unit

This section provides a block diagram of the clock generation control unit. For
information on the registers in the diagram, see "3.11.6 Registers in the Clock
Generation Control Unit".
Figure 3.11-1 Block Diagram of the Clock Generation Control Unit
X0
Oscillator
X1
circuit
Internal interrupt
Internal reset
The MB91260B series does not support the external bus mode.
76
[Clock generator]
DIVR0, DIVR1
registers
CLKR register
Main
oscillation
[Stop/sleep controller]
STCR register
[Reset source circuit]
INIT pin
RSRR register
[Watchdog controller]
CTBR register
TBCR register
CPU clock
frequency division
Peripheral clock
frequency division
External bus clock
frequency division
PLL
1/2
State
transition
control
Reset genera-
circuit
tion F/F
Reset genera-
tion F/F
Watchdog F/F
Time-base counter
Selector
Overflow detection F/F
Interrupt enable
CPU clock signal
Peripheral clock
signal
External bus
clock signal
Stop status
Sleep status
Internal reset (RST)
Internal reset (INIT)
Counter clock signal
Time-base timer
interrupt request