Fujitsu FR60 Hardware Manual page 158

CHAPTER 3 CPU AND CONTROL UNITS
■ Stop Mode
If "1" is set for bit7 (STOP bit) of the standby control register (STCR), stop mode is initiated and
the device enters the stop state. The stop state is maintained until a source for return from the
stop state occurs.
If "1" is set for both bit6 (SLEEP bit) and bit7 bit of the standby control register (STCR), bit7
(STOP bit) has precedence and the device enters the stop state.
For more information about the stop state, see "Stop State" in Section "3.13.1 Device States
and State Transitions".
[Stop mode transition]
Use the following sequences after using the synchronous standby mode (TBCR:Set by time
base counter control register bit8 SYNCS bit) when putting in the stop mode.
(LDI
(LDI
STB
LDUB @R12, R0
LDUB @R12, R0
NOP
NOP
NOP
NOP
NOP
Furthermore, set the I flag, ILM and ICR to ensure that branching into the interrupt handler
which is a return source occurs after returning to the standby mode.
❍ Circuits that stop in the stop state
• Oscillation circuits set to stop
If "1" is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clock
oscillation circuit in the stop state is stopped.
• PLL connected to the oscillation circuit that is either disabled or set to stop
If "1" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for bit10
(PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop
state is stopped.
• All internal circuits except those, described below, that do not stop in the stop state
❍ Circuits that do not stop in the stop state
• Oscillation circuits that are set not to stop
• If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clock
oscillation circuit in the stop state is not stopped.
• PLL connected to the oscillation circuit that is enabled and is not set to stop
• If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" is set for
bit10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the
stop state is not stopped.
138
#value_of_standby, R0)
#_STCR, R12)
R0, @R12
; value_of_standby is the writing data to STCR.
; _STCR is the address (481
; Writing in standby control register (STCR)
; STCR read for synchronous standby
; Dummy re-read of STCR
; five NOPs for timing adjustment
) of STCR.
H