Ppg Duty Set Register (Pdut:pdut3 To Pdut0) - Fujitsu FR60 Hardware Manual

7.3.3

PPG Duty Set Register (PDUT:PDUT3 to PDUT0)

The PDUT:PDUT3 to PDUT0 is a buffer register for setting duties. It has a buffer.
Transfers from the buffer are performed through counter borrows.
■ Bit Configuration of PPG Duty Set Register (PDUT:PDUT3 to PDUT0)
The bit configuration of the PDUT:PDUT3 to PDUT0 is shown below.
Figure 7.3-4 Bit Configuration of PPG Duty Set Register (PDUT:PDUT3 to PDUT0)
bit 15
Address: ch.0 000124
H
ch.1 00012C
H
ch.2 000134
H
ch.3 00013C
H
If the same value is written to the PCSR and PDUT, all-"H" is output for normal polarity and all-
"L" is output for reverse polarity.
Do not set values so that the condition PCSR < PDUT would be met. Otherwise, the PPG
output becomes undefined.
This register must be accessed in 16-bit data or 32-bit data.
W W W W
CHAPTER 7 PPG TIMER
0
W W W W
Initial value
XXXX
H
291